Improving FPGA Performance and Area Using an Adaptive Logic Module. - Michael D. Hutton; Jay Schleicher; David M. Lewis; Bruce Pedersen; Richard Yuan; Sinan Kaptanoglu; Gregg Baeckler; Boris Ratchev; Ketan Padalia; Mark Bourgeault; Andy Lee; Henry Kim; et al. (FPL, 2004)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

Efficient SAT-based Boolean matching for FPGA technology mapping. - Sean Safarpour; Andreas G. Veneris; Gregg Baeckler; Richard Yuan (DAC, 2006)

A methodology for FPGA to structured-ASIC synthesis and verification. - Michael D. Hutton; Richard Yuan; Jay Schleicher; Gregg Baeckler; Sammy Cheung; Kar Keng Chua; Hee Kong Phoo (DATE Designers' Forum, 2006)

HyperPipelining of High-Speed Interface Logic. - Gregg Baeckler (FPGA, 2016)

High Density and Performance Multiplication for FPGA. - Martin Langhammer; Gregg Baeckler (ARITH, 2018)

High Precision, High Performance FPGA Adders. - Martin Langhammer; Bogdan Pasca 001; Gregg Baeckler (FCCM, 2019)

Fractal Synthesis: Invited Tutorial. - Martin Langhammer; Gregg Baeckler; Sergey Gribok (FPGA, 2019)

Extracting INT8 Multipliers from INT18 Multipliers. - Martin Langhammer; Bogdan Pasca 001; Gregg Baeckler; Sergey Gribok (FPL, 2019)

High Performance Scalable FPGA Accelerator for Deep Neural Networks. - Sudarshan Srinivasan; Pradeep Janedula; Saurabh Dhoble; Sasikanth Avancha; Dipankar Das 002; Naveen Mellempudi; Bharat Daga; Martin Langhammer; Gregg Baeckler; Bharat Kaul (CoRR, 2019)

High Density 8-Bit Multiplier Systolic Arrays For Fpga. - Martin Langhammer; Sergey Gribok; Gregg Baeckler (FCCM, 2020)

High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA. - Martin Langhammer; Sergey Gribok; Gregg Baeckler (FPGA, 2020)

SpiderWeb - High Performance FPGA NoC. - Martin Langhammer; Gregg Baeckler; Sergey Gribok (IPDPS Workshops, 2020)

High Performance Soft Multi-Processor Arrays. - Martin Langhammer; Gregg Baeckler; Kim Bozman (ASAP, 2025)

A 950 MHz SIMT Soft Processor. - Martin Langhammer; Gregg Baeckler; Kim Bozman (IPDPS (Workshops), 2025)