Self-timed Ring based True Random Number Generator: Threat model and countermeasures. - Gregoire Gimenez; Abdelkarim Cherkaoui; Raphael Frisch; Laurent Fesquet (IVSW, 2017)

Static Timing Analysis of Asynchronous Bundled-Data Circuits. - Gregoire Gimenez; Abdelkarim Cherkaoui; Guillaume Cogniard; Laurent Fesquet (ASYNC, 2018)

The Arm Triple Core Lock-Step (TCLS) Processor. - Xabier Iturbe; Balaji Venu; Emre Ozer 001; Jean-Luc Poupat; Gregoire Gimenez; Hans-Ulrich Zurek (ACM Trans. Comput. Syst., 2018)

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. - Grégoire Gimenez; Jean Simatic; Laurent Fesquet (ASYNC, 2019)

A Self-Timed Ring based PUF. - Grégoire Gimenez; Abdelkarim Cherkaoui; Laurent Fesquet (ASYNC, 2020)