An 800-MHz embedded DRAM with a concurrent refresh mode. - Toshiaki Kirihata; Paul C. Parries; David R. Hanson; Hoki Kim; John Golz; Gregory Fredeman; Raj Rajeevakumar; John Griesemer; Norman Robson; Alberto Cestero; Babar A. Khan; Geng Wang; et al. (IEEE J. Solid State Circuits, 2005)

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (ISSCC, 2007)

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (IEEE J. Solid State Circuits, 2008)

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; William R. Reohr; Kavita Nair; Nianzheng Cao (ISSCC, 2010)

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; Toshiaki Kirihata; William R. Reohr; Kavita Nair; Nianzheng Cao (IEEE J. Solid State Circuits, 2011)

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; Michael A. Sperling; et al. (ISSCC, 2015)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

2.7 IBM z15: A 12-Core 5.2GHz Microprocessor. - Christopher J. Berry; Brian Bell 001; Adam Jatkowski; Jesse Surprise; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Dina Hamid; Chris Cavitt; Gregory Fredeman; Anthony Saporito; et al. (ISSCC, 2020)

IBM z15: Physical design improvements to significantly increase content in the same technology. - Christopher J. Berry; David Wolpert 001; Brian Bell 001; Adam Jatkowski; Jesse Surprise; Gerald Strevig; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Giora Biran; Dina Hamid; et al. (IBM J. Res. Dev., 2020)

Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. - David Wolpert 001; Christopher J. Berry; Brian Bell 001; Adam Jatkowski; Jesse Surprise; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Dina Hamid; Chris Cavitt; Gregory Fredeman; et al. (IEEE J. Solid State Circuits, 2021)