PowerPC AS A10 64-bit RISC microprocessor. - James W. Bishop; Michael J. Campion; Thomas L. Jeremiah; Stephen J. Mercier; Edmond J. Mohring; Kerry P. Pfarr; Bruce G. Rudolph; Gregory S. Still; Tennis S. White (IBM J. Res. Dev., 1996)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. - Phillip J. Restle; David Shan; David Hogenmiller; Yong Kim; Alan J. Drake; Jason Hibbeler; Thomas J. Bucelot; Gregory S. Still; Keith A. Jenkins; Joshua Friedrich (ISSCC, 2014)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric J. Fluhr; Gregory S. Still; Frank Campisano; Ian Carmichael; Eric Marz; Rahul Batra; Richard L. Willaman (ISSCC, 2022)

Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric Fluhr; Gregory S. Still; Francesco A. Campisano; Ian Charmichael; Eric Marz; Rahul Batra; Richard L. Willaman (IEEE J. Solid State Circuits, 2023)