Substrate noise-aware floorplanning for mixed-signal SOCs. - Marcin Jeske; Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske; Benyi Wang (ISCAS (2), 2004)

Substrate noise optimization in early floorplanning for mixed signal SOCs. - Grzegorz Blakiewicz; Marcin Jeske; Malgorzata Chrzanowska-Jeske (SoCC, 2004)

Substrate noise modeling in early floorplanning of MS-SOCs. - Grzegorz Blakiewicz; Marcin Jeske; Malgorzata Chrzanowska-Jeske; Jin S. Zhang (ASP-DAC, 2005)

Modeling of substrate noise block properties for early prediction. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (ISCAS (3), 2005)

Estimation of supply current spectrum for early noise evaluation. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (ISCAS, 2006)

Supply current spectrum estimation of digital cores at early design. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (IET Circuits Devices Syst., 2007)

Optimization of active circuits for substrate noise suppression. - Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske (ISCAS, 2008)

Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic. - Grzegorz Blakiewicz (IET Circuits Devices Syst., 2010)

Analog CMOS processor for early vision processing with highly reduced power consumption. - Waldemar Jendernalik; Jacek Jakusz; Grzegorz Blakiewicz; Robert Piotrowski; Stanislaw Szczepanski (ECCTD, 2011)

Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower. - Grzegorz Blakiewicz (IET Circuits Devices Syst., 2011)

An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing. - Waldemar Jendernalik; Grzegorz Blakiewicz; Jacek Jakusz; Stanislaw Szczepanski; Robert Piotrowski (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 0.5 V bulk-driven voltage follower/DC level shifter and its application in class AB output stage. - Tomasz Kulej; Grzegorz Blakiewicz (Int. J. Circuit Theory Appl., 2015)

A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array. - Miron Klosowski; Waldemar Jendernalik; Jacek Jakusz; Grzegorz Blakiewicz; Stanislaw Szczepanski (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Efficient Measurement System With Optimization Feature for Prototype CMOS Image Sensors. - Miron Klosowski; Jacek Jakusz; Waldemar Jendernalik; Grzegorz Blakiewicz; Stanislaw Szczepanski; Slawomir Koziel (IEEE Trans. Instrum. Meas., 2018)

Light-Powered Starter for Micro-Power Boost DC-DC Converter for CMOS Image Sensors. - Grzegorz Blakiewicz; Jacek Jakusz; Miron Klosowski; Waldemar Jendernalik; Stanislaw Szczepanski (Circuits Syst. Signal Process., 2020)

A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces. - Jacek Jakusz; Waldemar Jendernalik; Grzegorz Blakiewicz; Miron Klosowski; Stanislaw Szczepanski (Sensors, 2020)

Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager. - Grzegorz Blakiewicz; Miron Klosowski; Waldemar Jendernalik; Jacek Jakusz; Stanislaw Szczepanski (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors. - Miron Klosowski; Yichuang Sun; Waldemar Jendernalik; Grzegorz Blakiewicz; Jacek Jakusz; Stanislaw Szczepanski (IEEE Trans. Circuits Syst. II Express Briefs, 2023)