3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and Tezzaron. - Grzegorz Deptuch (3DIC, 2010)

Pixel detectors in 3D technologies for high energy physics. - Grzegorz Deptuch; Marcel Demarteau; Jim Hoff; Ronald Lipton; Alpana Shenai; Raymond Yarema; Tom Zimmerman 002 (3DIC, 2010)

Ultra fast X-ray detection systems in nanometer and 3D technologies. - Pawel Grybos; Aleksandra Drozd; Grzegorz Deptuch; Krzysztof Kasinski; Rafal Kleczek; Piotr Kmon; Piotr Maj; Piotr Otfmowski; Jacek Rauza; Robert Szczygiel; Tomasz Satlawa; Miroslaw Zoladz (MIXDES, 2014)

Pixellated readout IC: Analysis for single photon infrared detector for fast time of arrival applications. - Farah Fahim; Vala Fathipouri; Grzegorz Deptuch; Hooman Mohseni (ISCAS, 2015)

A content addressable memory with multi-Vdd scheme for low power tunable operation. - Siddhartha Joshi; Dawei Li; Seda Ogrenci Memik; Grzegorz Deptuch; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (MWSCAS, 2017)

Asynchronous Approximation of a Center of Gravity for Pixel Detectors' Readout Circuits. - Piotr Otfinowski; Grzegorz Deptuch; Piotr Maj (IEEE J. Solid State Circuits, 2018)

An Algorithm of an X-ray Hit Allocation to a Single Pixel in a Cluster and Its Test-Circuit Implementation. - Grzegorz Deptuch; Farah Fahim; Pawel Grybos; Jim Hoff; Scott Holm; Piotr Maj; David Peter Siddons; Piotr Kmon; Marcel Trimpl; Tom Zimmerman 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process. - Vamshi Manthena; Sandeep Miryala; Grzegorz Deptuch; Gabriella Carini (UEMCON, 2020)

Design and Challenges of Edge Computing ASICs on Front-End Electronics. - Sandeep Miryala; Gabriella Carini; Grzegorz Deptuch; Jin Huang; Srinivas Katkoori; Piotr Maj; Soumyajit Mandal; Yihui Ren 001; Md. Adnan Zaman (ISQED, 2022)

Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications. - Sandeep Miryala; Md. Adnan Zaman; Sandeep Mittal; Yihui Ren 001; Grzegorz Deptuch; Gabriella Carini; Sioan Zohar; Shinjae Yoo; Jack Fried; Jin Huang; Srinivas Katkoori (ISQED, 2022)

Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array. - Dominik Gorni; Grzegorz Deptuch; Sandeep Miryala (PRIME, 2022)

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines. - Nicholas St. John; Soumyajit Mandal; Grzegorz W. Deptuch; Eric Raguzin; Sergio Rescia (CoRR, 2022)

Self-Adaptation of Line Driver Pre-Emphasis Parameters via Embedded Line Loss Sensing. - Nicholas St. John; Soumyajit Mandal; Eric Raguzin; Piotr Maj; Grzegorz W. Deptuch (PRIME, 2023)

A Low-Power Data Link for Stitched Pixel Sensors. - Soumyajit Mandal; Grzegorz W. Deptuch; Md Arif Iqbal (MWSCAS, 2024)

Cryogenic Characterization of a 5-6 GHz LC VCO for CMOS-Quantum Co-Integration. - Rui Xu 008; Eric Raguzin; Soumyajit Mandal; Grzegorz W. Deptuch; Peter R. Kinget (QCE, 2024)

Automated and Holistic Co-design of Neural Networks and ASICs for Enabling In-Pixel Intelligence. - Shubha R. Kharel; Prashansa Mukim; Piotr Maj; Grzegorz W. Deptuch; Shinjae Yoo; Yihui Ren 001; Soumyajit Mandal (CoRR, 2024)

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals. - Prashansa Mukim; Gabriella A. Carini; Hucheng Chen; Grzegorz W. Deptuch; Shanshan Gao; Gianluigi De Geronimo; Soumyajit Mandal; Venkata Narasimha Manyam; Veljko Radeka; Sergio Rescia (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)