Hardware-Oriented Analysis of the Arithmetic Coding - Comparative Study of JPEG2000 and H.264/AVC Compression Standards. - Grzegorz Pastuszak (ICETE (3), 2004)

A high-performance architecture of arithmetic coder in JPEG2000. - Grzegorz Pastuszak (ICME, 2004)

A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding. - Grzegorz Pastuszak (PARELEC, 2004)

Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder. - Grzegorz Pastuszak (ICIAP, 2005)

A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000. - Grzegorz Pastuszak (ICME, 2005)

A high-performance architecture for embedded block coding in JPEG 2000. - Grzegorz Pastuszak (IEEE Trans. Circuits Syst. Video Technol., 2005)

A hardware-oriented analysis of arithmetic coding - comparative study of JPEG2000 and H.264/AVC comppression standards. - Grzegorz Pastuszak (e-Business and Telecommunication Networks, 2006)

Architecture Design for the Context Formatter in the H.264/AVC Encoder. - Grzegorz Pastuszak (DDECS, 2006)

Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding. - Grzegorz Pastuszak (PARELEC, 2006)

Multi-sequence H.264/AVC Rate Control Based on the Linear Model. - Grzegorz Pastuszak; Andrzej Pietrasiewicz (ICETE (Selected Papers), 2007)

Rate Control for Multi-Sequence H.264/AVC Compression. - Andrzej Pietrasiewicz; Grzegorz Pastuszak (SIGMAP, 2007)

Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression. - Grzegorz Pastuszak (SiPS, 2007)

Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection. - Grzegorz Pastuszak (ISVLSI, 2008)

Constant Bitrate Control for a Distributed Video Coding System. - Mariusz H. Jakubowski; João Ascenso; Grzegorz Pastuszak (SIGMAP, 2008)

A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC. - Grzegorz Pastuszak (IEEE Trans. Circuits Syst. Video Technol., 2008)

An Adaptive Computation-aware Algorithm for Multi-frame Variable Block-size Motion Estimation in H.264/AVC. - Mariusz H. Jakubowski; Grzegorz Pastuszak (SIGMAP, 2009)

Context-adaptive binary arithmetic decoder architecture for H.264/AVC. - Andrzej Abramowski; Grzegorz Pastuszak (PDeS, 2010)

Hardware implementation of the transformation module of the MPEG-4 AAC standard. - Grzegorz Brzuchalski; Grzegorz Pastuszak (PDeS, 2010)

Stream header decoder and context-adaptive variable-length decoder hardware module for H.264/AVC codec. - Grzegorz Pastuszak; Michal Wieczorek (PDeS, 2010)

Intra prediction hardware module for high-profile H.264/AVC decoder. - Mikolaj Roszkowski; Grzegorz Pastuszak (PDeS, 2010)

Data Reuse in Two-level Hierarchical Motion Estimation for High Resolution Video Coding. - Mariusz H. Jakubowski; Grzegorz Pastuszak (SIGMAP, 2010)

Hardware implementation of adaptive motion estimation and compensation for H.264/AVC. - Grzegorz Pastuszak; Mariusz H. Jakubowski (PCS, 2012)

A Novel Intra Prediction Architecture for the Hardware HEVC Encoder. - Andrzej Abramowski; Grzegorz Pastuszak (DSD, 2013)

Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder. - Grzegorz Pastuszak; Maciej Trochimiuk (DSD, 2013)

Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder. - Grzegorz Pastuszak; Mariusz H. Jakubowski (IEEE Trans. Circuits Syst. Video Technol., 2013)

A double-path intra prediction architecture for the hardware H.265/HEVC encoder. - Andrzej Abramowski; Grzegorz Pastuszak (DDECS, 2014)

FPGA architectures of the quantization and the dequantization for video encoders. - Grzegorz Pastuszak (DDECS, 2014)

FPGA design of the computation unit for the semi-global stereo matching algorithm. - Mikolaj Roszkowski; Grzegorz Pastuszak (DDECS, 2014)

Intra Prediction for the Hardware H.264/AVC High Profile Encoder. - Mikolaj Roszkowski; Grzegorz Pastuszak (J. Signal Process. Syst., 2014)

Flexible Architecture Design for H.265/HEVC Inverse Transform. - Grzegorz Pastuszak (Circuits Syst. Signal Process., 2015)

Hardware architectures for the H.265/HEVC discrete cosine transform. - Grzegorz Pastuszak (IET Image Process., 2015)

Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization. - Grzegorz Pastuszak (IEEE Trans. Circuits Syst. Video Technol., 2015)

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder. - Grzegorz Pastuszak; Maciej Trochimiuk (J. Real Time Image Process., 2016)

Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder. - Grzegorz Pastuszak; Maciej Trochimiuk (J. Real Time Image Process., 2016)

On a Criterion for Simultaneous Block-Diagonalization of Normal Matrices. - Grzegorz Pastuszak; Takeo Kamizawa; Andrzej Jamiolkowski (Open Syst. Inf. Dyn., 2016)

Algorithm and Architecture Design of the H.265/HEVC Intra Encoder. - Grzegorz Pastuszak; Andrzej Abramowski (IEEE Trans. Circuits Syst. Video Technol., 2016)

Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder. - Grzegorz Pastuszak; Mariusz H. Jakubowski (J. Signal Process. Syst., 2016)

Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders. - Grzegorz Pastuszak (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders. - Grzegorz Pastuszak (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Quantifier elimination theory and maps which preserve semipositivity. - Grzegorz Pastuszak; Adam Skowyrski; Andrzej Jamiolkowski (Quantum Inf. Process., 2021)

On One-Parameter Families of Hermiticity-Preserving Superoperators which Are Not Positive. - Grzegorz Pastuszak; Alicja Jaworska-Pastuszak; Takeo Kamizawa (Open Syst. Inf. Dyn., 2025)

Optimization of Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders. - Grzegorz Pastuszak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)