Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. - Guadalupe Miñana; Oscar Garnica; José Ignacio Hidalgo; Juan Lanchares; José Manuel Colmenar (PATMOS, 2005)

Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. - José Manuel Colmenar; Oscar Garnica; Juan Lanchares; José Ignacio Hidalgo; Guadalupe Miñana; Sonia López (DSD, 2006)

A Power-Aware Technique for Functional Units in High-Performance Processors. - Guadalupe Miñana; Oscar Garnica; José Ignacio Hidalgo; Juan Lanchares; José Manuel Colmenar (DSD, 2006)

Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. - José Manuel Colmenar; Oscar Garnica; Juan Lanchares; José Ignacio Hidalgo; Guadalupe Miñana; Sonia López (Euro-Par, 2006)

A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. - Guadalupe Miñana; José Ignacio Hidalgo; Oscar Garnica; Juan Lanchares; José Manuel Colmenar; Sonia López (PATMOS, 2006)

Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders. - Guadalupe Miñana; José Ignacio Hidalgo; Juan Lanchares; José Manuel Colmenar; Oscar Garnica; Sonia López (IET Comput. Digit. Tech., 2007)

Memories in Complutense Campus. - Victoria López; Matilde Santos Peñas; Guadalupe Miñana; Raquel Caro; Susanne Escobar-Torres Kraemmer; M. Sánchez Balmaseda; Guillermo Botella Juan (A Tribute to Prof. Dr. Da Ruan, 2013)

Enhancing Students' Learning Process Through Self-Generated Tests. - Marcos Sánchez-Élez; Inmaculada Pardines; Pablo García; Guadalupe Miñana; Sara Román Navarro; Margarita Sánchez; José L. Risco-Martín (CoRR, 2024)