Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. - Guan-Sing Chen; Chin-Yang Wu; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (A-SSCC, 2014)

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. - Ping-Chuan Chiang; Hao-Wei Hung; Hsiang-Yun Chu; Guan-Sing Chen; Jri Lee (ISSCC, 2014)

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. - Ping-Chuan Chiang; Jhih-Yu Jiang; Hao-Wei Hung; Chin-Yang Wu; Gaun-Sing Chen; Jri Lee (IEEE J. Solid State Circuits, 2015)