A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. - Ying-Zu Lin; Soon-Jyh Chang; Yen-Ting Liu; Chun-Cheng Liu; Guan-Ying Huang (ISSCC, 2009)

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. - Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; Chung-Ming Huang; Chih-Hao Huang; Linkai Bu; Chih-Chung Tsai (ISSCC, 2010)

Building Multi-kernel Embedded System on PAC Multi-core Platform. - Jing Chen; Chung-Ping Young; Da-Wei Chang; Guan-Ying Huang; Chung-Yuan Ke; Shih-Tun Yen; Tsang-Shuo Kuo (QSIC, 2010)

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. - Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin (IEEE J. Solid State Circuits, 2010)

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. - Ying-Zu Lin; Soon-Jyh Chang; Yen-Ting Liu; Chun-Cheng Liu; Guan-Ying Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. - Ying-Zu Lin; Soon-Jyh Chang; Ya-Ting Shyu; Guan-Ying Huang; Chun-Cheng Liu (A-SSCC, 2011)

Building a Multi-kernel Embedded System with High Performance IPC Mechanism. - Jing Chen; Da-Wei Chang; Chung-Ping Young; Guan-Ying Huang; Su-Lin Chu; Chung-Yuan Ke; Shih-Tun Yen; Tsang-Shuo Kuo (HPCC, 2011)

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology. - Sheng-Hsiung Lin; Jin-Fu Lin; Guan-Ying Huang; Soon-Jyh Chang (APCCAS, 2012)

A power-efficient sizing methodology of SAR ADCs. - Chun-Po Huang; Soon-Jyh Chang; Guan-Ying Huang; Cheng-Wu Lin (ISCAS, 2012)

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. - Ya-Ting Shyu; Ying-Zu Lin; Rong-Sing Chu; Guan-Ying Huang; Soon-Jyh Chang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. - Guan-Ying Huang; Soon-Jyh Chang; Chun-Cheng Liu; Ying-Zu Lin (IEEE J. Solid State Circuits, 2012)

A successive approximation ADC with resistor-capacitor hybrid structure. - Ting-Zi Chen; Soon-Jyh Chang; Guan-Ying Huang (VLSI-DAT, 2013)

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. - Ying-Zu Lin; Chun-Cheng Liu; Guan-Ying Huang; Ya-Ting Shyu; Yen-Ting Liu; Soon-Jyh Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. - Guan-Ying Huang; Soon-Jyh Chang; Chun-Cheng Liu; Ying-Zu Lin (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 10b 100kS/s SAR ADC with charge recycling switching method. - Kai-Hsiang Chiang; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin (A-SSCC, 2014)

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. - Cheng-Hsun Ho; Soon-Jyh Chang; Guan-Ying Huang; Che-Hsun Kuo (ISCAS, 2014)

Low power pipelined SAR ADC with loading-free architecture. - Jia-Jhang Wu; Soon-Jyh Chang; Sheng-Hsiung Lin; Chun-Po Huang; Guan-Ying Huang (VLSI-DAT, 2014)

Federated Learning Architecture for Bearing Fault Diagnosis. - Guan-Ying Huang; Ching-Hung Lee (ICSSE, 2021)

Industrial federated learning algorithm (P-PFedSGD) for tool wear estimation. - Guan-Ying Huang; Ching-Hung Lee (Future Gener. Comput. Syst., 2024)