Low power aging-aware register file design by duty cycle balancing. - Shuai Wang 006; Tao Jin; Chuanlei Zheng; Guangshan Duan (DATE, 2012)

Combating NBTI-induced aging in data caches. - Shuai Wang 006; Guangshan Duan; Chuanlei Zheng; Tao Jin (ACM Great Lakes Symposium on VLSI, 2013)

Exploiting narrow-width values for improving non-volatile cache lifetime. - Guangshan Duan; Shuai Wang 006 (DATE, 2014)

On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors. - Shuai Wang 006; Guangshan Duan (Microprocess. Microsystems, 2015)

Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing. - Shuai Wang 006; Tao Jin; Chuanlei Zheng; Guangshan Duan (J. Circuits Syst. Comput., 2016)

Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime. - Shuai Wang 006; Guangshan Duan; Yupeng Li; Qianhao Dong (ACM Trans. Design Autom. Electr. Syst., 2017)

On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. - Richard Bramley; Yanxiang Huang; Guangshan Duan; Nirmal R. Saxena; Paul Racunas (ITC, 2020)