Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. - Guangyi Lu; Yuan Wang 001; Jian Cao 002; Song Jia; Ganggang Zhang; Xing Zhang 002 (ASICON, 2013)

A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. - Jian Cao 002; Zhenxu Ye; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (ASICON, 2015)

Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. - Nan Han; Yuan Wang 001; Guangyi Lu; Jian Cao 002; Xing Zhang 002 (ASICON, 2015)

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Jian Cao 002; Song Jia; Xing Zhang 002 (Sci. China Inf. Sci., 2015)

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. - Guangyi Lu; Yuan Wang 001; Jian Cao 002; Song Jia; Xing Zhang 002 (ISCAS, 2016)

A compact SCR model using advanced BJT models and standard SPICE elements. - Jian Cao 002; Jingya Xu; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Jian Cao 002; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. - Yuan Wang 001; Guangyi Lu; Haibing Guo; Jian Cao 002; Song Jia; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

A novel SPICE circuit model of electrostatic discharge (ESD) generator. - Jian Cao 002; Yize Wang; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (IEICE Electron. Express, 2016)

Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. - Guangyi Lu; Yuan Wang 001; Xing Zhang 002 (IEICE Trans. Electron., 2016)

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. - Guangyi Lu; Yuan Wang 001; Yize Wang; Xing Zhang 002 (ISCAS, 2017)

A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. - Yize Wang; Yuan Wang 001; Guangyi Lu; Jian Cao 002; Xing Zhang 002 (IEICE Electron. Express, 2017)

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. - Yuan Wang 001; Guangyi Lu; Yize Wang; Xing Zhang 002 (IEICE Trans. Electron., 2017)

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Yize Wang; Ru Huang 001; Xing Zhang 002 (ISCAS, 2018)

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. - Yize Wang; Guangyi Lu; Yuan Wang 001 (IEEE Access, 2020)

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique. - Jiahao Wei; Weiqi Chen; Yajie Gong; Qi Wu; Guangyi Lu; Wei Gao; Lihui Wang; Mei Li; Haiming Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Microwave Network-Assisted Analysis and Machine Learning-Assisted Synthesis of Arbitrarily Tapped Coils and Its Application to On-Chip Ultrawideband ESD Protection Circuits. - Jiahao Wei; Weiqi Chen; Qi Wu; Guangyi Lu; Wei Gao; Lihui Wang; Mei Li; Haiming Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)