Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. - Xiangyu Dong 001; Xiaoxia Wu; Guangyu Sun 003; Yuan Xie 001; Hai Li 001; Yiran Chen 001 (DAC, 2008)

A Variation Aware High Level Synthesis Framework. - Feng Wang 004; Guangyu Sun 003; Yuan Xie 001 (DATE, 2008)

Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. - Hai Lin 004; Guangyu Sun 003; Yunsi Fei; Yuan Xie 001; Anand Sivasubramaniam (SASP, 2008)

Arithmetic unit design using 180nm TSV-based 3D stacking technology. - Jin Ouyang; Guangyu Sun 003; Yibo Chen; Lian Duan; Tao Zhang 032; Yuan Xie 001; Mary Jane Irwin (3DIC, 2009)

A criticality-driven microarchitectural three dimensional (3D) floorplanner. - Srinath Sridharan; Michael DeBole; Guangyu Sun 003; Yuan Xie 001; Vijaykrishnan Narayanan (ASP-DAC, 2009)

A novel architecture of the 3D stacked MRAM L2 cache for CMPs. - Guangyu Sun 003; Xiangyu Dong 001; Yuan Xie 001; Jian Li 059; Yiran Chen 001 (HPCA, 2009)

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. - Ahmed Al-Maashri; Guangyu Sun 003; Xiangyu Dong 001; Vijay Narayanan; Yuan Xie 001 (ICCD, 2009)

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. - Guangyu Sun 003; Xiaoxia Wu; Yuan Xie 001 (ISLPED, 2009)

Cost-driven 3D integration with interconnect layers. - Xiaoxia Wu; Guangyu Sun 003; Xiangyu Dong 001; Reetuparna Das; Yuan Xie 001; Chita R. Das; Jian Li 059 (DAC, 2010)

Energy- and endurance-aware design of phase change memory caches. - Yongsoo Joo; Dimin Niu; Xiangyu Dong 001; Guangyu Sun 003; Naehyuck Chang; Yuan Xie 001 (DATE, 2010)

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. - Guangyu Sun 003; Yongsoo Joo; Yibo Chen; Dimin Niu; Yuan Xie 001; Yiran Chen 001; Hai Li 001 (HPCA, 2010)

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. - Yiran Chen 001; Hai Li 001; Cheng-Kok Koh; Guangyu Sun 003; Jing Li 073; Yuan Xie 001; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Fabrication cost analysis for 2D, 2.5D, and 3D IC designs. - Chao Zhang 007; Guangyu Sun 003 (3DIC, 2011)

Using NEM relay to improve 3DIC cost efficiency. - Tao Zhang 032; Guangyu Sun 003 (3DIC, 2011)

A frequent-value based PRAM memory architecture. - Guangyu Sun 003; Dimin Niu; Jin Ouyang; Yuan Xie 001 (ASP-DAC, 2011)

Emerging non-volatile memories: opportunities and challenges. - Chun Jason Xue; Youtao Zhang; Yiran Chen 001; Guangyu Sun 003; Jianhua Joshua Yang; Hai Li 001 (CODES+ISSS, 2011)

Enabling architectural innovations using non-volatile memory. - Vijaykrishnan Narayanan; Vinay Saripalli; Karthik Swaminathan; Ravindhiran Mukundrajan; Guangyu Sun 003; Yuan Xie 001; Suman Datta (ACM Great Lakes Symposium on VLSI, 2011)

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. - Guangyu Sun 003; Eren Kursun; Jude A. Rivers; Yuan Xie 001 (ICCD, 2011)

Energy-efficient multi-level cell phase-change memory system with data encoding. - Jue Wang; Xiangyu Dong 001; Guangyu Sun 003; Dimin Niu; Yuan Xie 001 (ICCD, 2011)

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. - Asit K. Mishra; Xiangyu Dong 001; Guangyu Sun 003; Yuan Xie 001; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2011)

Moguls: a model to explore the memory hierarchy for bandwidth improvements. - Guangyu Sun 003; Christopher J. Hughes; Changkyu Kim; Jishen Zhao; Cong Xu 002; Yuan Xie 001; Yen-Kuang Chen (ISCA, 2011)

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. - Vinay Saripalli; Guangyu Sun 003; Asit K. Mishra; Yuan Xie 001; Suman Datta; Vijaykrishnan Narayanan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Three-dimensional Integrated Circuits: Design, EDA, and Architecture. - Guangyu Sun 003; Yibo Chen; Xiangyu Dong 001; Jin Ouyang; Yuan Xie 001 (Found. Trends Electron. Des. Autom., 2011)

Influence of Stacked 3D Memory/Cache Architectures on GPUs. - Ahmed Al-Maashri; Guangyu Sun 003; Xiangyu Dong 001; Yuan Xie 001; Narayanan Vijaykrishnan (3D Integration for NoC-based SoC Architectures, 2011)

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs. - Yibo Chen; Guangyu Sun 003; Qiaosha Zou; Yuan Xie 001 (DATE, 2012)

Modeling and design exploration of FBDRAM as on-chip memory. - Guangyu Sun 003; Cong Xu 002; Yuan Xie 001 (DATE, 2012)

Multi-level cell STT-RAM: Is it realistic or just a dream? - Yaojun Zhang; Lu Zhang; Wujie Wen; Guangyu Sun 003; Yiran Chen 001 (ICCAD, 2012)

Improving energy efficiency of write-asymmetric memories by log style write. - Guangyu Sun 003; Yaojun Zhang; Yu Wang 002; Yiran Chen 001 (ISLPED, 2012)

Energy-efficient GPU design with reconfigurable in-package graphics memory. - Jishen Zhao; Guangyu Sun 003; Gabriel H. Loh; Yuan Xie 001 (ISLPED, 2012)

Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs. - Guangyu Sun 003; Huazhong Yang; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

A Probabilistic Data Replacement Strategy for Flash-Based Hybrid Storage System. - Yanfei Lv; Xuexuan Chen; Guangyu Sun 003; Bin Cui 001 (APWeb, 2013)

An efficient run-time encryption scheme for non-volatile main memory. - Xian Zhang 001; Chao Zhang 007; Guangyu Sun 003; Jia Di; Tao Zhang 032 (CASES, 2013)

Asymmetric-access aware optimization for STT-RAM caches with process variations. - Yi Zhou; Chao Zhang 007; Guangyu Sun 003; Kun Wang; Yu Zhang (ACM Great Lakes Symposium on VLSI, 2013)

Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system. - Tao Zhang 032; Cong Xu 002; Yuan Xie 001; Guangyu Sun 003 (ICCD, 2013)

Designing scratchpad memory architecture with emerging STT-RAM memory technologies. - Peng Wang 025; Guangyu Sun 003; Tao Wang 004; Yuan Xie 001; Jason Cong (ISCAS, 2013)

Active SSD design for energy-efficiency improvement of web-scale data analysis. - Jian Ouyang; Shiding Lin; Zhenyu Hou; Peng Wang 025; Yong Wang; Guangyu Sun 003 (ISLPED, 2013)

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory. - Guangyu Sun 003; Eren Kursun; Jude A. Rivers; Yuan Xie 001 (ACM J. Emerg. Technol. Comput. Syst., 2013)

Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. - Jishen Zhao; Guangyu Sun 003; Gabriel H. Loh; Yuan Xie 001 (ACM Trans. Archit. Code Optim., 2013)

Prefetching techniques for STT-RAM based last-level cache in CMP systems. - Mengjie Mao; Guangyu Sun 003; Yong Li 009; Alex K. Jones; Yiran Chen 001 (ASP-DAC, 2014)

NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era. - Jia Zhan; Yuan Xie 001; Guangyu Sun 003 (DAC, 2014)

An efficient design and implementation of LSM-tree based key-value store on open-channel SSD. - Peng Wang 025; Guangyu Sun 003; Song Jiang 001; Jian Ouyang; Shiding Lin; Chen Zhang 001; Jason Cong (EuroSys, 2014)

3D-SWIFT: a high-performance 3D-stacked wide IO DRAM. - Tao Zhang 032; Cong Xu 002; Ke Chen 020; Guangyu Sun 003; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2014)

Adaptive placement and migration policy for an STT-RAM-based hybrid cache. - Zhe Wang 023; Daniel A. Jiménez; Cong Xu 002; Guangyu Sun 003; Yuan Xie 001 (HPCA, 2014)

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. - Tao Zhang 032; Matthew Poremba; Cong Xu 002; Guangyu Sun 003; Yuan Xie 001 (HPCA, 2014)

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. - Tao Zhang 032; Ke Chen 020; Cong Xu 002; Guangyu Sun 003; Tao Wang 004; Yuan Xie 001 (ISCA, 2014)

Rapid design space exploration of two-level unified caches. - Jingyu Deng; Yun Liang 001; Guojie Luo; Guangyu Sun 003 (ISCAS, 2014)

SBAC: a statistics based cache bypassing method for asymmetric-access caches. - Chao Zhang 007; Guangyu Sun 003; Peng Li 031; Tao Wang 004; Dimin Niu; Yiran Chen 001 (ISLPED, 2014)

GRT: A Reconfigurable SDR Platform with High Performance and Usability. - Tao Wang 004; Guangyu Sun 003; Jiahua Chen; Jian Gong; Haoyang Wu; Xiaoguang Li; Songwu Lu; Jason Cong (SIGARCH Comput. Archit. News, 2014)

Improving Memory Access Performance of In-Memory Key-Value Store Using Data Prefetching Techniques. - Pengfei Zhu; Guangyu Sun 003; Peng Wang 025; Mingyu Chen 001 (APPT, 2015)

InterFS: An Interplanted Distributed File System to Improve Storage Utilization. - Peng Wang 025; Le Cao; Chunbo Lai; Leqi Zou; Guangyu Sun 003; Jason Cong (APSys, 2015)

Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. - Chao Zhang 007; Guangyu Sun 003; Weiqi Zhang; Fan Mi; Hai Li 001; Weisheng Zhao (ASP-DAC, 2015)

A STT-RAM-based low-power hybrid register file for GPGPUs. - Gushu Li; Xiaoming Chen 003; Guangyu Sun 003; Henry Hoffmann; Yongpan Liu; Yu Wang 002; Huazhong Yang (DAC, 2015)

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes. - Hehe Li; Yongpan Liu; Qinghang Zhao; Yizi Gu; Xiao Sheng; Guangyu Sun 003; Chao Zhang 007; Meng-Fan Chang; Rong Luo; Huazhong Yang (DATE, 2015)

From device to system: cross-layer design exploration of racetrack memory. - Guangyu Sun 003; Chao Zhang 007; Hehe Li; Yue Zhang 010; Weiqi Zhang; Yizi Gu; Yinan Sun; Jacques-Olivier Klein; Dafine Ravelosona; Yongpan Liu; Weisheng Zhao; Huazhong Yang (DATE, 2015)

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. - Chen Zhang 001; Peng Li 031; Guangyu Sun 003; Yijin Guan; Bingjun Xiao; Jason Cong (FPGA, 2015)

Coordinated static and dynamic cache bypassing for GPUs. - Xiaolong Xie; Yun Liang 001; Yu Wang 002; Guangyu Sun 003; Tao Wang 004 (HPCA, 2015)

Hi-fi playback: tolerating position errors in shift operations of racetrack memory. - Chao Zhang 007; Guangyu Sun 003; Xian Zhang 001; Weiqi Zhang; Weisheng Zhao; Tao Wang 004; Yun Liang 001; Yongpan Liu; Yu Wang 002; Jiwu Shu (ISCA, 2015)

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system. - Yue Zhang 010; Chao Zhang 007; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun 003; Weisheng Zhao (ISCAS, 2015)

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations. - Shuangchen Li; Ang Li 005; Yuan Zhe; Yongpan Liu; Peng Li 001; Guangyu Sun 003; Yu Wang 002; Huazhong Yang; Yuan Xie 001 (ISLPED, 2015)

Enabling coordinated register allocation and thread-level parallelism optimization for GPUs. - Xiaolong Xie; Yun Liang 001; Xiuhong Li; Yudong Wu; Guangyu Sun 003; Tao Wang 004; Dongrui Fan (MICRO, 2015)

Fork path: improving efficiency of ORAM by removing redundant memory accesses. - Xian Zhang 001; Guangyu Sun 003; Chao Zhang 007; Weiqi Zhang; Yun Liang 001; Tao Wang 004; Yiran Chen 001; Jia Di (MICRO, 2015)

Atlas: Baidu's key-value storage system for cloud data. - Chunbo Lai; Song Jiang 001; Liqiong Yang; Shiding Lin; Guangyu Sun 003; Zhenyu Hou; Can Cui; Jason Cong (MSST, 2015)

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. - Bi Wu; Yuanqing Cheng; Ying Wang 001; Aida Todri-Sanial; Guangyu Sun 003; Lionel Torres; Weisheng Zhao (NANOARCH, 2015)

Exploring data placement in racetrack memory based scratchpad memory. - Haiyu Mao; Chao Zhang 007; Guangyu Sun 003; Jiwu Shu (NVMSA, 2015)

An Efficient Compiler Framework for Cache Bypassing on GPUs. - Yun Liang 001; Xiaolong Xie; Guangyu Sun 003; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Performance-centric register file design for GPUs using racetrack memory. - Shuo Wang 009; Yun Liang 001; Chao Zhang 007; Xiaolong Xie; Guangyu Sun 003; Yongpan Liu; Yu Wang 002; Xiuhong Li (ASP-DAC, 2016)

A novel PUF based on cell error rate distribution of STT-RAM. - Xian Zhang 001; Guangyu Sun 003; Yaojun Zhang; Yiran Chen 001; Hai Li 001; Wujie Wen; Jia Di (ASP-DAC, 2016)

Pin Tumbler Lock: A shift based encryption mechanism for racetrack memory. - Hongbin Zhang; Chao Zhang 007; Xian Zhang 001; Guangyu Sun 003; Jiwu Shu (ASP-DAC, 2016)

PDS: pseudo-differential sensing scheme for STT-MRAM. - Wang Kang 001; Tingting Pang; Bi Wu; Weifeng Lv; Youguang Zhang; Guangyu Sun 003; Weisheng Zhao (DAC, 2016)

Exploring Main Memory Design Based on Racetrack Memory Technology. - Qingda Hu; Guangyu Sun 003; Jiwu Shu; Chao Zhang 007 (ACM Great Lakes Symposium on VLSI, 2016)

The Applications of NVM Technology in Hardware Security. - Chaofei Yang; Beiye Liu; Yandan Wang; Yiran Chen 001; Hai Li 001; Xian Zhang 001; Guangyu Sun 003 (ACM Great Lakes Symposium on VLSI, 2016)

NXgraph: An efficient graph processing system on a single machine. - Yuze Chi; Guohao Dai; Yu Wang 002; Guangyu Sun 003; Guoliang Li 001; Huazhong Yang (ICDE, 2016)

Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. - Chen Zhang 001; Di Wu 010; Jiayu Sun; Guangyu Sun 003; Guojie Luo; Jason Cong (ISLPED, 2016)

np-ECC: Nonadjacent position error correction code for racetrack memory. - Xiaoyang Wang 006; Chao Zhang 007; Xian Zhang 001; Guangyu Sun 003 (NANOARCH, 2016)

Accelerate context switch by racetrack-SRAM hybrid cells. - Weiqi Zhang; Chao Zhang 007; Guangyu Sun 003 (NANOARCH, 2016)

Statistical Cache Bypassing for Non-Volatile Memory. - Guangyu Sun 003; Chao Zhang 007; Peng Li 031; Tao Wang 004; Yiran Chen 001 (IEEE Trans. Computers, 2016)

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. - Yue Zhang 010; Chao Zhang 007; Jiang Nan; Zhizhong Zhang 004; Xueying Zhang; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun 003; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

FPGA-based accelerator for long short-term memory recurrent neural networks. - Yijin Guan; Zhihang Yuan; Guangyu Sun 003; Jason Cong (ASP-DAC, 2017)

Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns. - Xian Zhang 001; Guangyu Sun 003 (DAC, 2017)

SPMS: Strand based persistent memory system. - Shuo Li 007; Peng Wang 025; Nong Xiao 001; Guangyu Sun 003; Fang Liu 002 (DATE, 2017)

Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss. - Haiyu Mao; Xian Zhang 001; Guangyu Sun 003; Jiwu Shu (DATE, 2017)

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. - Yijin Guan; Hao Liang 003; Ningyi Xu; Wenqiang Wang; Shaoshuai Shi; Xi Chen 107; Guangyu Sun 003; Wei Zhang 012; Jason Cong (FCCM, 2017)

Reducing Overfitting in Deep Convolutional Neural Networks Using Redundancy Regularizer. - Bingzhe Wu; Zhichao Liu; Zhihang Yuan; Guangyu Sun 003; Charles Wu (ICANN (2), 2017)

SRPGAN: Perceptual Generative Adversarial Network for Single Image Super Resolution. - Bingzhe Wu; Haodong Duan; Zhichao Liu; Guangyu Sun 003 (CoRR, 2017)

Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective. - Wang Kang 001; Liang Chang 002; Zhaohao Wang; Weifeng Lv; Guangyu Sun 003; Weisheng Zhao (IEEE Trans. Computers, 2017)

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes. - Yongpan Liu; Jinshan Yue; Hehe Li; Qinghang Zhao; Mengying Zhao; Chun Jason Xue; Guangyu Sun 003; Meng-Fan Chang; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases. - Peng Wang 025; Shuo Li 007; Guangyu Sun 003; Xiaoyang Wang 006; Yiran Chen 001; Hai Li 001; Jason Cong; Nong Xiao 001; Tao Zhang 032 (HPCA, 2018)

PM3: Power Modeling and Power Management for Processing-in-Memory. - Chao Zhang 007; Tong Meng; Guangyu Sun 003 (HPCA, 2018)

Path Prefetching: Accelerating Index Searches for In-Memory Databases. - Shuo Li 007; Zhiguang Chen 001; Nong Xiao 001; Guangyu Sun 003 (ICCD, 2018)

Shadow Block: Accelerating ORAM Accesses with Data Duplication. - Xian Zhang 001; Guangyu Sun 003; Peichen Xie; Chao Zhang 007; Yannan Liu; Lingxiao Wei; Qiang Xu 001; Chun Jason Xue (MICRO, 2018)

V-PIM: An Analytical Overhead Model for Processing-in-Memory Architectures. - Peichen Xie; Guangyu Sun 003; Feng Wang 046; Guojie Luo (NVMSA, 2018)

CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs. - Xiaolong Xie; Yun Liang 001; Xiuhong Li; Yudong Wu; Guangyu Sun 003; Tao Wang 004; Dongrui Fan (IEEE Trans. Computers, 2018)

Optimizing Cache Bypassing and Warp Scheduling for GPUs. - Yun Liang 001; Xiaolong Xie; Yu Wang 002; Guangyu Sun 003; Tao Wang 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

G2C: A Generator-to-Classifier Framework Integrating Multi-Stained Visual Cues for Pathological Glomerulus Classification. - Bingzhe Wu; Xiaolu Zhang; Shiwan Zhao; Lingxi Xie; Caihong Zeng; Zhihong Liu; Guangyu Sun 003 (AAAI, 2019)

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Peng Huang 004; Jinfeng Kang (ASAP, 2019)

P3SGD: Patient Privacy Preserving SGD for Regularizing Deep CNNs in Pathological Image Classification. - Bingzhe Wu; Shiwan Zhao; Guangyu Sun 003; Xiaolu Zhang; Zhong Su; Caihong Zeng; Zhihong Liu (CVPR, 2019)

ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory. - Zheng Liang 003; Guangyu Sun 003; Wang Kang 001; Xing Chen; Weisheng Zhao (DAC, 2019)

Accelerate service live migration in resource-limited edge computing systems. - Zhe Zhou 002; Xintong Li; Guangyu Sun 003 (SEC, 2019)

BAYHENN: Combining Bayesian Deep Learning and Homomorphic Encryption for Secure DNN Inference. - Peichen Xie; Bingzhe Wu; Guangyu Sun 003 (IJCAI, 2019)

Generalization in Generative Adversarial Networks: A Novel Perspective from Privacy Protection. - Bingzhe Wu; Shiwan Zhao; Chaochao Chen 001; Haoyang Xu; Li Wang 056; Xiaolu Zhang; Guangyu Sun 003; Jun Zhou 011 (NeurIPS, 2019)

Joint Task Assignment, Transmission, and Computing Resource Allocation in Multilayer Mobile Edge Computing Systems. - Pengfei Wang 005; Chao Yao; Zijie Zheng; Guangyu Sun 003; Lingyang Song (IEEE Internet Things J., 2019)

EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond. - Chao Yao; Xiaoyang Wang 006; Zijie Zheng; Guangyu Sun 003; Lingyang Song (IEEE Netw., 2019)

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses. - Shuo Li 007; Nong Xiao 001; Peng Wang 025; Guangyu Sun 003; Xiaoyang Wang 006; Yiran Chen 001; Hai Helen Li; Jason Cong; Tao Zhang 032 (IEEE Trans. Computers, 2019)

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. - Guohao Dai; Tianhao Huang; Yuze Chi; Jishen Zhao; Guangyu Sun 003; Yongpan Liu; Yu Wang 002; Yuan Xie 001; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. - Chen Zhang 001; Guangyu Sun 003; Zhenman Fang; Peipei Zhou 001; Peichen Pan; Jason Cong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Characterizing Membership Privacy in Stochastic Gradient Langevin Dynamics. - Bingzhe Wu; Chaochao Chen 001; Shiwan Zhao; Cen Chen 001; Yuan Yao; Guangyu Sun 003; Li Wang 056; Xiaolu Zhang; Jun Zhou 011 (AAAI, 2020)

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. - Zhao Wang; Yijin Guan; Guangyu Sun 003; Dimin Niu; Yuhao Wang 002; Hongzhong Zheng; Yinhe Han 001 (ACA, 2020)

Hardware-assisted Service Live Migration in Resource-limited Edge Computing Systems. - Zhe Zhou 002; Xintong Li; Xiaoyang Wang 006; Zheng Liang 003; Guangyu Sun 003; Guojie Luo (DAC, 2020)

S2DNAS: Transforming Static CNN Model for Dynamic Inference via Neural Architecture Search. - Zhihang Yuan; Bingzhe Wu; Guangyu Sun 003; Zheng Liang 003; Shiwan Zhao; Weichen Bi (ECCV (2), 2020)

SaFace: Towards Scenario-aware Face Recognition via Edge Computing System. - Zhe Zhou 002; Bingzhe Wu; Zheng Liang 003; Guangyu Sun 003; Chenren Xu; Guojie Luo (HotEdge, 2020)

MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block. - Qilin Zheng; Xingchen Li; Zongwei Wang 001; Guangyu Sun 003; Yimao Cai; Ru Huang 001; Yiran Chen 001; Hai Li 001 (ICCAD, 2020)

Edge-Stream: a Stream Processing Approach for Distributed Applications on a Hierarchical Edge-computing System. - Xiaoyang Wang 006; Zhe Zhou 002; Ping Han; Tong Meng; Guangyu Sun 003; Jidong Zhai (SEC, 2020)

ENAS4D: Efficient Multi-stage CNN Architecture Search for Dynamic Inference. - Zhihang Yuan; Xin Liu 073; Bingzhe Wu; Guangyu Sun 003 (CoRR, 2020)

Customizing Trusted AI Accelerators for Efficient Privacy-Preserving Machine Learning. - Peichen Xie; Xuanle Ren; Guangyu Sun 003 (CoRR, 2020)

Preface. - Wen-Guang Chen; Ying-Wei Luo; Guang-Yu Sun 003 (J. Comput. Sci. Technol., 2020)

Bigflow: A General Optimization Layer for Distributed Computing Frameworks. - Yuncong Zhang; Xiaoyang Wang 006; Cong Wang; Yao Xu; Jian-Wei Zhang; Xiaodong Lin; Guangyu Sun 003; Gong-Lin Zheng; Shan-Hui Yin; Xian-Jin Ye; Li Li; Zhan Song; et al. (J. Comput. Sci. Technol., 2020)

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. - Yijin Guan; Guangyu Sun 003; Zhihang Yuan; Xingchen Li; Ningyi Xu; Shu Chen; Jason Cong; Yuan Xie 001 (IEEE Trans. Computers, 2020)

Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses. - Jingchen Zhu; Guangyu Sun 003; Xian Zhang 001; Chao Zhang 007; Weiqi Zhang; Yun Liang 001; Tao Wang 004; Yiran Chen 001; Jia Di (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks. - Spencer Nelson; Sang Yun Kim 002; Jia Di; Zhe Zhou 002; Zhihang Yuan; Guangyu Sun 003 (ASYNC, 2021)

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. - Zhe Zhou 002; Bizhao Shi; Zhe Zhang 006; Yijin Guan; Guangyu Sun 003; Guojie Luo (DAC, 2021)

Rapid Configuration of Asynchronous Recurrent Neural Networks for ASIC Implementations. - Spencer Nelson; Wassim Khalil; SangYun Kim 002; Jia Di; Zhe Zhou 002; Zhihang Yuan; Guang-Yu Sun 003 (HPEC, 2021)

SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes. - Feng Wang 046; Guangyu Sun 003; Guojie Luo (ICCAD, 2021)

PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture. - Ye Zhang; Shuo Wang 009; Xian Zhang 001; Jiangbin Dong; Xingzhong Mao; Fan Long; Cong Wang; Dong Zhou 006; Mingyu Gao 001; Guangyu Sun 003 (ISCA, 2021)

NAS4RRAM: neural network architecture search for inference on RRAM-based accelerators. - Zhihang Yuan; Jingze Liu; Xingchen Li; Longhao Yan; Haoxiang Chen 003; Bingzhe Wu; Yuchao Yang 001; Guangyu Sun 003 (Sci. China Inf. Sci., 2021)

Agatha: Smart Contract for DNN Computation. - Zihan Zheng; Peichen Xie; Xian Zhang 001; Shuo Chen 001; Yang Chen; Xiaobing Guo; Guangzhong Sun; Guangyu Sun 003; Lidong Zhou (CoRR, 2021)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators. - Zhao Wang; Guangyu Sun 003; Jingchen Zhu; Zhe Zhou 002; Yijiang Guo; Zhihang Yuan (CoRR, 2021)

PTQ-SL: Exploring the Sub-layerwise Post-training Quantization. - Zhihang Yuan; Yiqi Chen; Chenhao Xue; Chenguang Zhang; Qiankun Wang; Guangyu Sun 003 (CoRR, 2021)

Energon: Towards Efficient Acceleration of Transformers Using Dynamic Sparse Attention. - Zhe Zhou 002; Junlin Liu; Zhenyu Gu; Guangyu Sun 003 (CoRR, 2021)

GCNear: A Hybrid Architecture for Efficient GCN Training with Near-Memory Processing. - Zhe Zhou 002; Cong Li; Xuechao Wei; Guangyu Sun 003 (CoRR, 2021)

PTQ4ViT: Post-Training Quantization Framework for Vision Transformers. - Zhihang Yuan; Chenhao Xue; Yiqi Chen; Qiang Wu 012; Guangyu Sun 003 (CoRR, 2021)

Area Efficient Pattern Representation of Binary Neural Networks on RRAM. - Feng Wang 046; Guojie Luo; Guang-Yu Sun 003; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (J. Comput. Sci. Technol., 2021)

CIB-HIER: Centralized Input Buffer Design in Hierarchical High-radix Routers. - Cunlu Li; Dezun Dong; Shazhou Yang; Xiangke Liao; Guangyu Sun 003; Yongheng Liu (ACM Trans. Archit. Code Optim., 2021)

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Jinfeng Kang; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

GNNear: Accelerating Full-Batch Training of Graph Neural Networks with near-Memory Processing. - Zhe Zhou 002; Cong Li; Xuechao Wei; Xiaoyang Wang 006; Guangyu Sun 003 (PACT, 2022)

A Mapping Model of SNNs to Neuromorphic Hardware. - Xiuping Cui; Xiaochen Hao; Yun Liang 001; Guangyu Sun 003; Xiaoxin Cui; Yuan Wang 001; Ru Huang 001 (AICAS, 2022)

Tailor: removing redundant operations in memristive analog neural network accelerators. - Xingchen Li; Zhihang Yuan; Guangyu Sun 003; Liang Zhao; Zhichao Lu (DAC, 2022)

PTQ4ViT: Post-training Quantization for Vision Transformers with Twin Uniform Quantization. - Zhihang Yuan; Chenhao Xue; Yiqi Chen; Qiang Wu 012; Guangyu Sun 003 (ECCV (12), 2022)

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. - Xingchen Li; Bingzhe Wu; Guangyu Sun 003; Zhe Zhang 006; Zhihang Yuan; Runsheng Wang; Ru Huang 001; Dimin Niu; Hongzhong Zheng; Zhichao Lu; Liang Zhao; Meng-Fan Marvin Chang; et al. (HPCA, 2022)

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Zhixuan Wang; Wei He; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Meng Wu 005; Hao Zhang 119; Peng Zhou; Jinguang Liu; Guangyu Sun 003; Jiayoon Ru; et al. (ISSCC, 2022)

Latency-aware Spatial-wise Dynamic Networks. - Yizeng Han; Zhihang Yuan; Yifan Pu; Chenhao Xue; Shiji Song; Guangyu Sun 003; Gao Huang 001 (NeurIPS, 2022)

GNNSampler: Bridging the Gap Between Sampling Algorithms of GNN and Hardware. - Xin Liu 073; Mingyu Yan; Shuhan Song; Zhengyang Lv; Wenming Li; Guangyu Sun 003; Xiaochun Ye; Dongrui Fan (ECML/PKDD (5), 2022)

PetS: A Unified Framework for Parameter-Efficient Transformers Serving. - Zhe Zhou 002; Xuechao Wei; Jiejing Zhang; Guangyu Sun 003 (USENIX ATC, 2022)

A Survey of Trustworthy Graph Learning: Reliability, Explainability, and Privacy Protection. - Bingzhe Wu; Jintang Li; Junchi Yu; Yatao Bian; Hengtong Zhang; Chaochao Chen 001; Chengbin Hou; Guoji Fu; Liang Chen 001; Tingyang Xu; Yu Rong 001; Xiaolin Zheng; et al. (CoRR, 2022)

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. - Xingchen Li; Zhihang Yuan; Yijin Guan; Guangyu Sun 003; Tao Zhang 032; Rongshan Wei; Dimin Niu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. - Qilin Zheng; Xingchen Li; Yijin Guan; Zongwei Wang 001; Yimao Cai; Yiran Chen 001; Guangyu Sun 003; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

The Case for FPGA-Based Edge Computing. - Chenren Xu; Shuang Jiang; Guojie Luo; Guangyu Sun 003; Ning An 001; Gang Huang 001; Xuanzhe Liu (IEEE Trans. Mob. Comput., 2022)

Editorial for the special issue on memory architectures and systems for modern applications. - Guangyu Sun 003; Liang Shi 001; Jingtong Hu (CCF Trans. High Perform. Comput., 2022)

Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. - Chen Zhang 001; Guangyu Sun 003; Zhenman Fang; Peipei Zhou 001; Jason Cong (ACM TUR-C, 2023)

Polaris: Enhancing CXL-based Memory Expanders with Memory-side Prefetching. - Zhe Zhou 002; Shuotao Xu; Yiqi Chen; Tao Zhang 032; Ran Shu 001; Lei Qu; Peng Cheng 005; Yongqiang Xiong; Guangyu Sun 003 (APPT, 2023)

NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction. - Cong Li; Zhe Zhou 002; Xingchen Li; Guangyu Sun 003; Dimin Niu (DAC, 2023)

DIMM-Link: Enabling Efficient Inter-DIMM Communication for Near-Memory Processing. - Zhe Zhou 002; Cong Li; Fan Yang 093; Guangyu Sun 003 (HPCA, 2023)

TileFlow: A Framework for Modeling Fusion Dataflow via Tree-based Analysis. - Size Zheng 001; Siyuan Chen 007; Siyuan Gao; Liancheng Jia; Guangyu Sun 003; Runsheng Wang; Yun Liang 001 (MICRO, 2023)

Benchmarking the Reliability of Post-training Quantization: a Particular Focus on Worst-case Performance. - Zhihang Yuan; Jiawei Liu 006; Jiaxiang Wu 001; Dawei Yang; Qiang Wu 012; Guangyu Sun 003; Wenyu Liu 001; Xinggang Wang; Bingzhe Wu (CoRR, 2023)

RPTQ: Reorder-based Post-training Quantization for Large Language Models. - Zhihang Yuan; Lin Niu; Jiawei Liu 006; Wenyu Liu 001; Xinggang Wang; Yuzhang Shang; Guangyu Sun 003; Qiang Wu 012; Jiaxiang Wu 001; Bingzhe Wu (CoRR, 2023)

ASVD: Activation-aware Singular Value Decomposition for Compressing Large Language Models. - Zhihang Yuan; Yuzhang Shang; Yue Song; Qiang Wu 012; Yan Yan 002; Guangyu Sun 003 (CoRR, 2023)

Energon: Toward Efficient Acceleration of Transformers Using Dynamic Sparse Attention. - Zhe Zhou 002; Junlin Liu; Zhenyu Gu; Guangyu Sun 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Sky-Sorter: A Processing-in-Memory Architecture for Large-Scale Sorting. - Farzaneh Zokaee; Fan Chen 001; Guangyu Sun 003; Lei Jiang 001 (IEEE Trans. Computers, 2023)

COPPER: a combinatorial optimization problem solver with processing-in-memory architecture. - Qiankun Wang; Xingchen Li; Bingzhe Wu; Ke Yang; Wei Hu; Guangyu Sun 003; Yuchao Yang 001 (Frontiers Inf. Technol. Electron. Eng., 2023)

FD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications. - Xiaoyang Wang 006; Zhe Zhou 002; Zhihang Yuan; Jingchen Zhu; Yulong Cao; Yao Zhang; Kangrui Sun; Guangyu Sun 003 (ACM Trans. Embed. Comput. Syst., 2023)

PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization. - Cong Li; Zhe Zhou 002; Yang Wang 053; Fan Yang 093; Ting Cao; Mao Yang 004; Yun Liang 001; Guangyu Sun 003 (ASPLOS (2), 2024)

SpecPIM: Accelerating Speculative Inference on PIM-Enabled System via Architecture-Dataflow Co-Exploration. - Cong Li; Zhe Zhou 002; Size Zheng 001; Jiaxi Zhang 001; Yun Liang 001; Guangyu Sun 003 (ASPLOS (3), 2024)

A Software-Hardware Co-design Solution for 3D Inner Structure Reconstruction. - Xingchen Li; Zhe Zhou 002; Qilin Zheng; Guangyu Sun 003; Qiankun Wang; Chenhao Xue (DAC, 2024)

Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. - Chenhao Xue; Chen Zhang 001; Xun Jiang 002; Zhutianya Gao; Yibo Lin; Guangyu Sun 003 (DAC, 2024)

Algorithm-Hardware Co-Design for Energy-Efficient A/D Conversion in ReRAM-Based Accelerators. - Chenguang Zhang; Zhihang Yuan; Xingchen Li; Guangyu Sun 003 (DATE, 2024)

StreamPIM: Streaming Matrix Computation in Racetrack Memory. - Yuda An; Yunxiao Tang; Shushu Yi; Li Peng; Xiurui Pan; Guangyu Sun 003; Zhaochu Luo; Qiao Li 001; Jie Zhang 048 (HPCA, 2024)

OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. - Fan Cui; Chenyang Yin; Kexing Zhou; Youwei Xiao; Guangyu Sun 003; Qiang Xu 001; Qipeng Guo; Yun Liang 001; Xingcheng Zhang; Demin Song; Dahua Lin (ICCAD, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering. - Zhe Zhou 002; Yiqi Chen; Tao Zhang 032; Yang Wang 053; Ran Shu 001; Shuotao Xu; Peng Cheng 005; Lei Qu; Yongqiang Xiong; Jie Zhang 048; Guangyu Sun 003 (MICRO, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

LLM Inference Unveiled: Survey and Roofline Model Insights. - Zhihang Yuan; Yuzhang Shang; Yang Zhou; Zhen Dong 003; Zhe Zhou 002; Chenhao Xue; Bingzhe Wu; Zhikai Li; Qingyi Gu; Yong Jae Lee; Yan Yan 002; Beidi Chen; et al. (CoRR, 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

Toward CXL-Native Memory Tiering via Device-Side Profiling. - Zhe Zhou 002; Yiqi Chen; Tao Zhang 032; Yang Wang 053; Ran Shu 001; Shuotao Xu; Peng Cheng 005; Lei Qu; Yongqiang Xiong; Guangyu Sun 003 (CoRR, 2024)

Theseus: Towards High-Efficiency Wafer-Scale Chip Design Space Exploration for Large Language Models. - Jingchen Zhu; Chenhao Xue; Yiqi Chen; Zhao Wang; Guangyu Sun 003 (CoRR, 2024)

OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. - Fan Cui; Chenyang Yin; Kexing Zhou; Youwei Xiao; Guangyu Sun 003; Qiang Xu 001; Qipeng Guo; Demin Song; Dahua Lin; Xingcheng Zhang; Yun Liang 001 (CoRR, 2024)

CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators. - Lixia Han; Renjie Pan 003; Zheng Zhou; Hairuo Lu; Yiyang Chen; Haozhang Yang; Peng Huang 004; Guangyu Sun 003; Xiaoyan Liu; Jinfeng Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing. - Zhao Wang; Yiqi Chen; Cong Li; Yijin Guan; Dimin Niu; Tianchan Guan; Zhaoyang Du; Xingda Wei; Guangyu Sun 003 (ASPLOS (2), 2025)

UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures. - Tongxin Xie; Zhenhua Zhu; Bing Li; Yukai He; Cong Li; Guangyu Sun 003; Huazhong Yang; Yuan Xie 001; Yu Wang 002 (HPCA, 2025)

H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference. - Cong Li; Yihan Yin; Xintong Wu; Jingchen Zhu; Zhutianya Gao; Dimin Niu; Qiang Wu 012; Xin Si; Yuan Xie 001; Chen Zhang 001; Guangyu Sun 003 (ISCA, 2025)

AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM. - Yuanpeng Zhang; Xing Hu 010; Xi Chen 107; Zhihang Yuan; Cong Li; Jingchen Zhu; Zhao Wang; Chenguang Zhang; Xin Si; Wei Gao; Qiang Wu 012; Runsheng Wang; et al. (ISCA, 2025)

Enabling Efficient Transaction Processing on CXL-Based Memory Sharing. - Zhao Wang; Yiqi Chen; Cong Li; Dimin Niu; Tianchan Guan; Zhaoyang Du; Xingda Wei; Guangyu Sun 003 (CoRR, 2025)

FPGA-based Emulation and Device-Side Management for CXL-based Memory Tiering Systems. - Yiqi Chen; Xiping Dong; Zhe Zhou 002; Zhao Wang; Jie Zhang 048; Guangyu Sun 003 (CoRR, 2025)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators. - Chenhao Xue; Yi Ren; Jinwei Zhou; Kezhi Li; Chen Zhang 001; Yibo Lin; Lining Zhang; Qiang Xu 001; Guangyu Sun 003 (CoRR, 2025)

DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization. - Yi Ren; Chenhao Xue; Jiaxing Zhang; Chen Zhang 001; Qiang Xu 001; Yibo Lin; Lining Zhang; Guangyu Sun 003 (CoRR, 2025)

ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA. - Zhengyuan Shi; Zeju Li; Chengyu Ma; Yunhao Zhou; Ziyang Zheng; Jiawei Liu 006; Hongyang Pan; Lingfeng Zhou; Kezhi Li; Jiaying Zhu; Lingwei Yan; Zhiqiang He; et al. (CoRR, 2025)

AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models. - Chenhao Xue; Kezhi Li; Jiaxing Zhang; Yi Ren; Zhengyuan Shi; Chen Zhang 001; Yibo Lin; Lining Zhang; Qiang Xu 001; Guangyu Sun 003 (CoRR, 2025)

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. - Chenchen Zhao; Zhengyuan Shi; Xiangyu Wen; Chengjie Liu; Yi Liu; Yunhao Zhou; Yuxiang Zhao; Hefei Feng; Yinan Zhu; Gwok-Waa Wan; Xin Cheng; Weiyu Chen; et al. (CoRR, 2025)

Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference. - Chen Zhang 001; Shijie Cao; Guohao Dai; Chenbo Geng; Zhuliang Yao; Wencong Xiao; Yunxin Liu 001; Ming Wu 007; Lintao Zhang; Guangyu Sun 003; Zhigang Ji; Runsheng Wang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)