A 40 μV VRipple, 0.1-ps FoM Output-Capacitor-Less Fully Time-Domain Digital LDO With a VCO-Assisted Dual Loop. - Guanzhe Hu; Shengping Lv; Yufei Song; Peng Zhang; Wen Jia; Fei Chen; Shuqiang Lu; Zhihua Wang; Hanjun Jiang (ISCAS, 2026)

A Low Noise Bio-potential AFE Achieving 300-mV EDO Tolerance and <20-ms-Settling with VCO-based Full Digital DC Servo Loop. - Shengping Lv; Guanzhe Hu; Liuxin Lv; Peng Zhang; Fei Chen 006; Wen Jia; Shuqiang Lu; Zhihua Wang 001; Hanjun Jiang (ISCAS, 2026)