Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology. - Guerric de Streel; David Bol (ISLPED, 2013)

A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range. - David Bol; Guerric de Streel; François Botman; Angelo Kuti Lusala; Numa Couniot (VLSIC, 2014)

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. - Numa Couniot; Guerric de Streel; François Botman; Angelo Kuti Lusala; Denis Flandre; David Bol (IEEE J. Solid State Circuits, 2015)

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. - Thomas Haine; François Stas; Guerric de Streel; Cecilia Gimeno; Denis Flandre; David Bol (ICDSC, 2016)

Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools. - François Stas; Guerric de Streel; David Bol (NEWCAS, 2016)

Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers. - Dina Kamel; Guerric de Streel; Santos Merino Del Pozo; Kashif Nawaz; François-Xavier Standaert; Denis Flandre; David Bol (SPACE, 2016)

SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape. - Guerric de Streel; François Stas; Thibaut Gurne; François Durant; Charlotte Frenkel; David Bol (VLSI Circuits, 2016)

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. - Guerric de Streel; François Stas; Thibaut Gurne; François Durant; Charlotte Frenkel; Andreia Cathelin; David Bol (IEEE J. Solid State Circuits, 2017)