Challenges in code generation for embedded processors. - Guido Araujo; Srinivas Devadas; Kurt Keutzer; Stan Y. Liao; Sharad Malik; Ashok Sudarsanam; Steven W. K. Tjiang; Albert R. Wang (Code Generation for Embedded Processors, 1994)

Optimal code generation for embedded memory non-homogeneous register architectures. - Guido Araujo; Sharad Malik (ISSS, 1995)

Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. - Guido Araujo; Sharad Malik; Mike Tien-Chien Lee (DAC, 1996)

Instruction Set Design and Optimizations for Address Computation in DSP Architectures. - Guido Araujo; Ashok Sudarsanam; Sharad Malik (ISSS, 1996)

Code Compression Based on Operand Factorization. - Guido Araujo; Paulo Centoducatte; Mario Lúcio Côrtes; Ricardo Pannain (MICRO, 1998)

Code generation for fixed-point DSPs. - Guido Araujo; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 1998)

Compressed Code Execution on DSP Architectures. - Paulo Centoducatte; Ricardo Pannain; Guido Araujo (ISSS, 1999)

Array Reference Allocation Using SSA-Form and Live Range Growth. - Marcelo Silva Cintra; Guido Araujo (LCTES, 2000)

Expression-tree-based algorithms for code compression on embedded RISC architectures. - Guido Araujo; Paulo Centoducatte; Rodolfo Azevedo; Ricardo Pannain (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. - Marcio Buss; Rodolfo Azevedo; Paulo Centoducatte; Guido Araujo (CASES, 2001)

Optimal Live Range Merge for Address Register Allocation in Embedded Programs. - Guilherme Ottoni; Sandro Rigo; Guido Araujo; Subramanian Rajagopalan; Sharad Malik (CC, 2001)

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. - Subramanian Rajagopalan; Sreeranga P. Rajan; Sharad Malik; Sandro Rigo; Guido Araujo; Koichiro Takayama (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. - Guido Araujo; Sharad Malik; Zhining Huang; Nahri Moreano (ISSS, 2002)

Global array reference allocation. - Guido Araujo; Guilherme Ottoni; Marcelo Silva Cintra (ACM Trans. Design Autom. Electr. Syst., 2002)

Mixed static/dynamic profiling for dictionary based code compression. - Eduardo Braulio Wanderley Netto; Rodolfo Azevedo; Paulo Centoducatte; Guido Araujo (SoC, 2003)

Exploring Memory Hierarchy with ArchC. - Pablo Viana; Edna Barros; Sandro Rigo; Rodolfo Azevedo; Guido Araujo (SBAC-PAD, 2003)

Improving Offset Assignment through Simultaneous Variable Coalescing. - Desiree Ottoni; Guilherme Ottoni; Guido Araujo; Rainer Leupers (SCOPES, 2003)

Address register allocation for arrays in loops of embedded programs. - Guilherme Ottoni; Guido Araujo (Microelectron. J., 2003)

Multi-profile based code compression. - Eduardo Braulio Wanderley Netto; Rodolfo Azevedo; Paulo Centoducatte; Guido Araujo (DAC, 2004)

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. - Pablo Viana; Edna Barros; Sandro Rigo; Rodolfo Azevedo; Guido Araujo (DATE, 2004)

Fast instruction set custornization. - Edson Borin; Felipe Klein; Nahri Moreano; Rodolfo Azevedo; Guido Araujo (ESTIMedia, 2004)

Optimizations for Compiled Simulation Using Instruction Type Information. - Marcus Bartholomeu; Rodolfo Azevedo; Sandro Rigo; Guido Araujo (SBAC-PAD, 2004)

Multi-Profile Instruction Based Compression. - Eduardo Braulio Wanderley Netto; Rodolfo Azevedo; Paulo Centoducatte; Guido Araujo (SBAC-PAD, 2004)

ArchC: A SystemC-Based Architecture Description Language. - Sandro Rigo; Guido Araujo; Marcus Bartholomeu; Rodolfo Azevedo (SBAC-PAD, 2004)

An automatic testbench generation tool for a SystemC functional verification methodology. - Karina R. G. da Silva; Elmar U. K. Melcher; Guido Araujo; Valdiney Alves Pimenta (SBCCI, 2004)

Teaching computer architecture using an architecture description language. - Sandro Rigo; Marcio Juliato; Rodolfo Azevedo; Guido Araujo; Paulo Centoducatte (WCAE, 2004)

The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation. - Cid C. de Souza; André M. Lima; Nahri Moreano; Guido Araujo (WEA, 2004)

The design of dynamically reconfigurable datapath coprocessors. - Zhining Huang; Sharad Malik; Nahri Moreano; Guido Araujo (ACM Trans. Embed. Comput. Syst., 2004)

Processor Centric Specification and Modelling of MPSoCs. - Cristiano C. de Araújo; Edna Barros; Rodolfo Azevedo; Guido Araujo (FDL, 2005)

A custom instruction approach for hardware and software implementations of finite field arithmetic over F263 using Gaussian normal bases. - Marcio Juliato; Guido Araujo; Julio César López-Hernández; Ricardo Dahab (FPT, 2005)

High-Level Switching Activity Prediction Through Sampled Monitored Simulation. - Felipe Klein; Rodolfo Azevedo; Guido Araujo (SoC, 2005)

Design of a decompressor engine on a SPARC processor. - Eduardo Afonso Billo; Rodolfo Azevedo; Guido Araujo; Paulo Centoducatte; Eduardo Braulio Wanderley Netto (SBCCI, 2005)

A SystemC-only design methodology and the CINE-IP multimedia platform. - Guido Araujo; Edna Barros; Elmar U. K. Melcher; Rodolfo Azevedo; Karina R. G. da Silva; Bruno O. Prado; Manoel Eusébio de Lima (Des. Autom. Embed. Syst., 2005)

Platform designer: An approach for modeling multiprocessor platforms based on SystemC. - Cristiano C. de Araújo; Millena Gomes; Edna Barros; Sandro Rigo; Rodolfo Azevedo; Guido Araujo (Des. Autom. Embed. Syst., 2005)

The ArchC Architecture Description Language and Tools. - Rodolfo Azevedo; Sandro Rigo; Marcus Bartholomeu; Guido Araujo; Cristiano C. de Araújo; Edna Barros (Int. J. Parallel Program., 2005)

The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation. - Cid C. de Souza; André M. Lima; Guido Araujo; Nahri Moreano (ACM J. Exp. Algorithmics, 2005)

Dynamic binary control-flow errors detection. - Edson Borin; Cheng Wang 013; Youfeng Wu; Guido Araujo (SIGARCH Comput. Archit. News, 2005)

Efficient datapath merging for partially reconfigurable architectures. - Nahri Moreano; Edson Borin; Cid C. de Souza; Guido Araujo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

2D-VLIW: An Architecture Based on the Geometry of Computation. - Ricardo Santos 002; Rodolfo Azevedo; Guido Araujo (ASAP, 2006)

Software-Based Transparent and Comprehensive Control-Flow Error Detection. - Edson Borin; Cheng Wang 013; Youfeng Wu; Guido Araujo (CGO, 2006)

Clustering-Based Microcode Compression. - Edson Borin; Maurício Breternitz Jr.; Youfeng Wu; Guido Araujo (ICCD, 2006)

Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. - Ricardo Santos 002; Rodolfo Azevedo; Guido Araujo (IPDPS, 2006)

Offset assignment using simultaneous variable coalescing. - Desiree Ottoni; Guilherme Ottoni; Guido Araujo; Rainer Leupers (ACM Trans. Embed. Comput. Syst., 2006)

A computational reflection mechanism to support platform debugging in SystemC. - Bruno C. Albertini; Sandro Rigo; Guido Araujo; Cristiano C. de Araújo; Edna Barros; Willians Azevedo (CODES+ISSS, 2007)

The Image Forest Transform Architecture. - Fabio Augusto Cappabianco; Guido Araujo; Alexandre X. Falcão (FPT, 2007)

A multi-model power estimation engine for accuracy optimization. - Felipe Klein; Guido Araujo; Rodolfo Azevedo; Roberto Leao; Luiz C. V. dos Santos (ISLPED, 2007)

On the Limitations of Power Macromodeling Techniques. - Felipe Klein; Guido Araujo; Rodolfo Azevedo; Roberto Leao; Luiz C. V. dos Santos (ISVLSI, 2007)

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. - Richard Maciel; Bruno C. Albertini; Sandro Rigo; Guido Araujo; Rodolfo Azevedo (ISVLSI, 2007)

A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. - Fernando Kronbauer; Alexandro Baldassin; Bruno C. Albertini; Paulo Centoducatte; Sandro Rigo; Guido Araujo; Rodolfo Azevedo (IEEE International Workshop on Rapid System Prototyping, 2007)

A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases. - Marcio Juliato; Guido Araujo; Julio López 002; Ricardo Dahab (J. VLSI Signal Process., 2007)

Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor. - Ricardo Santos 002; Rodolfo Azevedo; Guido Araujo (J. Univers. Comput. Sci., 2008)

On the energy-efficiency of software transactional memory. - Felipe Klein; Alexandro Baldassin; Guido Araujo; Paulo Centoducatte; Rodolfo Azevedo (SBCCI, 2009)

Characterizing the Energy Consumption of Software Transactional Memory. - Alexandro Baldassin; Felipe Klein; Guido Araujo; Rodolfo Azevedo; Paulo Centoducatte (IEEE Comput. Archit. Lett., 2009)

A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization. - Felipe Klein; Roberto Leao; Guido Araujo; Luiz C. V. dos Santos; Rodolfo Azevedo (IEEE Trans. Very Large Scale Integr. Syst., 2009)

T-DRE: a hardware trusted computing base for direct recording electronic vote machines. - Roberto Gallo; Henrique Kawakami; Ricardo Dahab; Rafael Azevedo; Saulo Lima; Guido Araujo (ACSAC, 2010)

Reducing False Aborts in STM Systems. - Daniel Nicácio; Guido Araujo (ICA3PP (1), 2010)

Trace Execution Automata in Dynamic Binary Translation. - João Paulo Porto; Guido Araujo; Edson Borin; Youfeng Wu (ISCA Workshops, 2010)

ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation. - Maxwell Souza; Daniel Nicácio; Guido Araujo (ISCA Workshops, 2010)

LUTS: A Lightweight User-Level Transaction Scheduler. - Daniel Nicácio; Alexandro Baldassin; Guido Araujo (ICA3PP (1), 2011)

Structure-Constrained Microcode Compression. - Edson Borin; Guido Araujo; Maurício Breternitz Jr.; Youfeng Wu (SBAC-PAD, 2011)

Exploring Dynamic Program Behavior with Frames and Phases. - Divino Cesar S. Lucas; Guido Araujo; Edson Borin (WSCAD-SSC, 2012)

Computational reflection and its application to platform verification. - Bruno C. Albertini; Sandro Rigo; Guido Araujo (Des. Autom. Embed. Syst., 2012)

Data center power and performance optimization through global selection of P-states and utilization rates. - Reinaldo A. Bergamaschi; Leonardo Piga; Sandro Rigo; Rodolfo Azevedo; Guido Araújo (Sustain. Comput. Informatics Syst., 2012)

Cache-based cross-iteration coherence for speculative parallelization. - Andre Baixo; João Paulo Porto; Guido Araujo (HiPC, 2013)

Transaction scheduling using conflict avoidance and Contention Intensity. - Márcio Machado Pereira; Alexandro Baldassin; Guido Araujo; Luiz Eduardo Buzato (HiPC, 2013)

Modeling virtual machines misprediction overhead. - Divino Cesar S. Lucas; Rafael Auler; Rafael Dalibera; Sandro Rigo; Edson Borin; Guido Araujo (IISWC, 2013)

Transaction Scheduling Using Dynamic Conflict Avoidance. - Daniel Nicácio; Alexandro Baldassin; Guido Araujo (Int. J. Parallel Program., 2013)

Extending decoupled software pipeline to parallelize Java programs. - André Loureiro; João Paulo Porto; Guido Araujo (Softw. Pract. Exp., 2013)

Wear-out analysis of Error Correction Techniques in Phase-Change Memory. - Caio Hoffman; Luiz Ramos; Rodolfo Azevedo; Guido Araujo (DATE, 2014)

Measuring Effective Work to Reward Success in Dynamic Transaction Scheduling. - Márcio Machado Pereira; José Nelson Amaral; Guido Araujo (ICPP, 2014)

Loop-Carried Dependence Verification in OpenMP. - Juan Salamanca 001; Luis Mattos; Guido Araujo (IWOMP, 2014)

Multi-dimensional Evaluation of Haswell's Transactional Memory Performance. - Márcio Machado Pereira; Matthew Gaudet; José Nelson Amaral; Guido Araujo (SBAC-PAD, 2014)

Cloud-based OpenMP Parallelization Using a MapReduce Runtime. - Rodolfo Wottrich; Rodolfo Azevedo; Guido Araujo (SBAC-PAD, 2014)

Microcode Compression Using Structured-Constrained Clustering. - Edson Borin; Guido Araujo; Maurício Breternitz Jr.; Youfeng Wu (Int. J. Parallel Program., 2014)

Computer security by hardware-intrinsic authentication. - Caio Hoffman; Mario Lúcio Côrtes; Diego F. Aranha; Guido Araujo (CODES+ISSS, 2015)

The Batched DOACROSS loop parallelization algorithm. - Divino Cesar S. Lucas; Guido Araujo (HPCS, 2015)

Performance implications of dynamic memory allocators on transactional memory systems. - Alexandro Baldassin; Edson Borin; Guido Araujo (PPoPP, 2015)

Serialization Management for Best-Effort Hardware Transactional Memory. - Matthew Gaudet; Guido Araujo; José Nelson Amaral (SBAC-PAD, 2015)

Using Hardware Transactional Memory to Enable Speculative Trace Optimization. - Juan Salamanca 001; José Nelson Amaral; Guido Araujo (SBAC-PAD (Workshops), 2015)

Improving the Statistical Variability of Delay-based Physical Unclonable Functions. - Jefferson Capovilla; Mario Lúcio Côrtes; Guido Araujo (SBCCI, 2015)

Guest Editorial: SBAC-PAD 2013. - Guido Araujo; Jean-Luc Gaudiot; Manish Parashar; Derek Chiou; José Nelson Amaral; Chita R. Das (Int. J. Parallel Program., 2015)

Cylindrical Reconvergence Physical Unclonable Function. - Rodrigo C. Surita; Mario Lúcio Côrtes; Diego F. Aranha; Guido Araujo (DSD, 2016)

Task parallel programming model + hardware acceleration = performance advantage. - Tamer Dallou; Divino Cesar Soares Lucas; Guido Araujo; Lucas Morais; Eduardo Ferreira Barbosa; Michael Frank 008; Richard Bagley; Raj Sayana (Hot Chips Symposium, 2016)

Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. - Juan Salamanca 001; José Nelson Amaral; Guido Araujo (IPDPS, 2016)

Automatic Insertion of Copy Annotation in Data-Parallel Programs. - Gleison Souza Diniz Mendonca; Breno Campos Ferreira Guimarães; Péricles Rafael Oliveira Alves; Fernando Magno Quintão Pereira; Márcio Machado Pereira; Guido Araujo (SBAC-PAD, 2016)

Parallel Computation for the All-Pairs Suffix-Prefix Problem. - Felipe A. Louza; Simon Gog; Leandro Zanotto; Guido Araujo; Guilherme P. Telles (SPIRE, 2016)

Study of hardware transactional memory characteristics and serialization policies on Haswell. - Márcio Machado Pereira; Matthew Gaudet; José Nelson Amaral; Guido Araujo (Parallel Comput., 2016)

Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories. - Juan Salamanca 001; José Nelson Amaral; Guido Araujo (Euro-Par, 2017)

The Cloud as an OpenMP Offloading Device. - Hervé Yviquel; Guido Araujo (ICPP, 2017)

Revisiting phased transactional memory. - Joao P. L. de Carvalho; Guido Araujo; Alexandro Baldassin (ICS, 2017)

Compiling and Optimizing OpenMP 4.X Programs to OpenCL and SPIR. - Márcio Machado Pereira; Rafael C. F. Sousa; Guido Araujo (IWOMP, 2017)

Data Coherence Analysis and Optimization for Heterogeneous Computing. - Rafael Cardoso Fernandes Sousa; Márcio Machado Pereira; Fernando Magno Quintão Pereira; Guido Araujo (SBAC-PAD, 2017)

Automatic Scan Parallelization in OpenMP. - Maicol Zegarra; Márcio Machado Pereira; Xavier Martorell; Guido Araujo (SBAC-PAD (Workshops), 2017)

DawnCC: Automatic Annotation for Data Parallelism and Offloading. - Gleison Souza Diniz Mendonca; Breno Campos Ferreira Guimarães; Péricles Alves; Márcio Machado Pereira; Guido Araujo; Fernando Magno Quintão Pereira (ACM Trans. Archit. Code Optim., 2017)

Automatic annotation of tasks in structured code. - Pedro Ramos; Gleison Souza Diniz Mendonca; Divino Soares; Guido Araújo; Fernando Magno Quintão Pereira (PACT, 2018)

Automatic Offloading of Cluster Accelerators. - Ciro Ceissler; Ramon Nepomuceno; Márcio Machado Pereira; Guido Araujo (FCCM, 2018)

DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability. - Luis Mattos; Divino Cesar S. Lucas; Juan Salamanca 001; Joao P. L. de Carvalho; Márcio Machado Pereira; Guido Araujo (SBAC-PAD, 2018)

Automatic Ray-Tracer Cloud Offloading in OPENMP. - Matheus Mortatti; Hervé Yviquel; Guido Araujo (SBAC-PAD, 2018)

High performance collision cross section calculation - HPCCS. - Leandro Zanotto; Gabriel Heerdt; Paulo C. T. Souza; Guido Araujo; Munir S. Skaf (J. Comput. Chem., 2018)

CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence. - Rodrigo C. Surita; Mario Lúcio Côrtes; Diego F. Aranha; Guido Araujo (Microprocess. Microsystems, 2018)

Cluster Programming using the OpenMP Accelerator Model. - Hervé Yviquel; Lauro Cruz; Guido Araujo (ACM Trans. Archit. Code Optim., 2018)

Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation. - Juan Salamanca 001; José Nelson Amaral; Guido Araujo (IEEE Trans. Parallel Distributed Syst., 2018)

Circumventing Uniqueness of XOR Arbiter PUFs. - Caio Hoffman; Catherine H. Gebotys; Diego F. Aranha; Mario Lúcio Côrtes; Guido Araújo (DSD, 2019)

Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor. - Lucas Morais; Vitor Silva; Alfredo Goldman; Carlos Álvarez 001; Jaume Bosch; Michael Frank 008; Guido Araujo (MICRO, 2019)

Data-flow analysis and optimization for data coherence in heterogeneous architectures. - Rafael C. F. Sousa; Márcio Machado Pereira; Fernando Magno Quintão Pereira; Guido Araujo (J. Parallel Distributed Comput., 2019)

The Case for Phase-Based Transactional Memory. - Joao P. L. de Carvalho; Guido Araujo; Alexandro Baldassin (IEEE Trans. Parallel Distributed Syst., 2019)

NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory. - Alexandro Baldassin; Rafael Murari; João P. L. de Carvalho; Guido Araujo; Daniel Castro 004; João Barreto 001; Paolo Romano 002 (Euro-Par, 2020)

Improving Transactional Code Generation via Variable Annotation and Barrier Elision. - João P. L. de Carvalho; Bruno C. Honorio; Alexandro Baldassin; Guido Araujo (IPDPS, 2020)

Using OpenMP to Detect and Speculate Dynamic DOALL Loops. - Bruno Chinelato Honorio; João P. L. de Carvalho; Munir S. Skaf; Guido Araujo (IWOMP, 2020)

OmpTracing: Easy Profiling of OpenMP Programs. - Vitoria Pinho; Hervé Yviquel; Márcio Machado Pereira; Guido Araujo (SBAC-PAD, 2020)

Acceleration Opportunities in Linear Algebra Applications via Idiom Recognition. - João P. L. de Carvalho; Braedy Kuzma; Guido Araujo (ICPE Companion, 2020)

Accelerating Graph Applications Using Phased Transactional Memory. - Catalina Munoz Morales; Rafael Murari; Joao P. L. de Carvalho; Bruno Chinelato Honorio; Alexandro Baldassin; Guido Araujo (Euro-Par, 2021)

Enabling OpenMP Task Parallelism on Multi-FPGAs. - Ramon Nepomuceno; Renan Sterle; Guilherme Valarini; Márcio Machado Pereira; Hervé Yviquel; Guido Araujo (FCCM, 2021)

Pooling Acceleration in the DaVinci Architecture Using Im2col and Col2im Instructions. - Caio S. Rohwedder; João P. L. de Carvalho; José Nelson Amaral; Guido Araújo; Giancarlo Colmenares; Kai-Ting Amy Wang (IPDPS Workshops, 2021)

Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation. - Catalina Munoz Morales; Bruno C. Honorio; Alexandro Baldassin; Guido Araujo (SBAC-PAD, 2021)

Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling. - Rafael C. F. Sousa; Byungmin Jung; Jaehwa Kwak; Michael Frank 008; Guido Araujo (SBAC-PAD, 2021)

KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls. - João P. L. de Carvalho; Braedy Kuzma; Ivan Korostelev; José Nelson Amaral; Christopher Barton; José E. Moreira; Guido Araujo (ACM Trans. Archit. Code Optim., 2021)

Improving Convolution via Cache Hierarchy Tiling and Reduced Packing. - Victor Ferrari; Rafael C. F. Sousa; Márcio Machado Pereira; João P. L. de Carvalho; José Nelson Amaral; Guido Araujo (PACT, 2022)

The OpenMP Cluster Programming Model. - Hervé Yviquel; Márcio Machado Pereira; Emilio Francesquini; Guilherme Valarini; Gustavo Leite; Pedro Henrique Di Francia Rosso; Rodrigo Ceccato; Carla Cusihualpa; Vitoria Dias; Sandro Rigo; Alan Souza; Guido Araujo (ICPP Workshops, 2022)

Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization. - Samuel Cajahuaringa; Leandro N. Zanotto; Daniel L. Z. Caetano; Sandro Rigo; Hervé Yviquel; Munir S. Skaf; Guido Araujo (SBAC-PAD, 2022)

An OpenMP-only Linear Algebra Library for Distributed Architectures. - Carla Cardoso; Hervé Yviquel; Guilherme Valarini; Gustavo Leite; Rodrigo Ceccato; Márcio Machado Pereira; Alan Souza; Guido Araujo (SBAC-PADW, 2022)

Implementing the Broadcast Operation in a Distributed Task-based Runtime. - Rodrigo Ceccato; Hervé Yviquel; Márcio Machado Pereira; Alan Souza; Guido Araujo (SBAC-PADW, 2022)

Source Matching and Rewriting. - Vinícius Couto Espindola; Luciano G. Zago; Hervé Yviquel; Guido Araújo (CoRR, 2022)

Special Issue on Compiling for Accelerators. - Guido Araujo; Lucas Wanner 001 (IEEE Micro, 2022)

Using Barrier Elision to Improve Transactional Code Generation. - Bruno Chinelato Honorio; João P. L. de Carvalho; Catalina Munoz Morales; Alexandro Baldassin; Guido Araujo (ACM Trans. Archit. Code Optim., 2022)

On the impact of mode transition on phased transactional memory performance. - Catalina Munoz Morales; Bruno C. Honorio; Joao P. L. de Carvalho; Alexandro Baldassin; Guido Araujo (J. Parallel Distributed Comput., 2023)

Tensor slicing and optimization for multicore NPUs. - Rafael C. F. Sousa; Márcio Machado Pereira; Yongin Kwon; Taeho Kim; Namsoon Jung; Chang Soo Kim; Michael Frank 008; Guido Araujo (J. Parallel Distributed Comput., 2023)

MassCCS: A High-Performance Collision Cross-Section Software for Large Macromolecular Assemblies. - Samuel Cajahuaringa; Daniel L. Z. Caetano; Leandro N. Zanotto; Guido Araujo; Munir S. Skaf (J. Chem. Inf. Model., 2023)

Source Matching and Rewriting for MLIR Using String-Based Automata. - Vinícius Couto Espindola; Luciano G. Zago; Hervé Yviquel; Guido Araujo (ACM Trans. Archit. Code Optim., 2023)

Fast matrix multiplication via compiler-only layered data reorganization and intrinsic lowering. - Braedy Kuzma; Ivan Korostelev; João P. L. de Carvalho; José E. Moreira; Christopher Barton; Guido Araujo; José Nelson Amaral (Softw. Pract. Exp., 2023)

Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions. - Victor Ferrari; Rafael Cardoso Fernandes Sousa; Márcio Machado Pereira; Joao P. L. de Carvalho; José Nelson Amaral; José E. Moreira; Guido Araujo (ACM Trans. Archit. Code Optim., 2023)

Combining Compression and Prefetching to Improve Checkpointing for Inverse Seismic Problems in GPUs. - Thiago Maltempi; Sandro Rigo; Márcio Machado Pereira; Hervé Yviquel; Jessé Costa; Guido Araujo (Euro-Par (3), 2024)

Integrating Multi-FPGA Acceleration to OpenMP Distributed Computing. - Pedro Henrique Di Francia Rosso; Lucian Petrica; Nusrat Jahan Lisa; Márcio Machado Pereira; Sandro Rigo; Hervé Yviquel; Vanderlei Bonato; Emilio Francesquini; Guido Araujo (IWOMP, 2024)

DeepWave: A Software Stack for Parallelizing Deep Learning Models Used in Geophysics. - Allan Pinto; Gustavo Leite; Márcio Machado Pereira; Hervé Yviquel; Sandro Rigo; Guido Araujo (SBAC-PAD, 2024)

Towards an Optimized Heterogeneous Distributed Task Scheduler in OpenMP Cluster. - Rémy Neveu; Rodrigo Ceccato; Gustavo Leite; Guido Araujo; Jose Manuel Monsalve Diaz; Hervé Yviquel (SC Workshops, 2024)

ConvBench: A Comprehensive Benchmark for 2D Convolution Primitive Evaluation. - Lucas Alvarenga; Victor Ferrari; Rafael Souza; Márcio Machado Pereira; Guido Araujo (CoRR, 2024)

Ion-molecule collision cross-section calculations using trajectory parallelization in distributed systems. - Samuel Cajahuaringa; Leandro N. Zanotto; Sandro Rigo; Hervé Yviquel; Munir S. Skaf; Guido Araujo (J. Parallel Distributed Comput., 2024)

Enabling HW-Based Task Scheduling in Large Multicore Architectures. - Lucas Morais; Carlos Álvarez 001; Daniel Jiménez-González; Juan Miguel De Haro Ruiz; Guido Araujo; Michael Frank 008; Alfredo Goldman; Xavier Martorell (IEEE Trans. Computers, 2024)

Scalable OpenMP Remote Offloading via Asynchronous MPI and Coroutine-Driven Communication. - Jhonatan Cléto; Guilherme Valarini; Márcio Machado Pereira; Guido Araujo; Hervé Yviquel (Euro-Par (3), 2025)