Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits. - Johan S. Witters; Guido Groeseneken; Herman E. Maes (IEEE J. Solid State Circuits, 1989)

Novel level-identifying circuit for flash multilevel memories. - Donato Montanari; Jan Van Houdt; Guido Groeseneken; Herman E. Maes (IEEE J. Solid State Circuits, 1998)

Cost-effective cleaning and high-quality thin gate oxides. - Marc M. Heyns; Twan Bearda; Ingrid Cornelissen; Stefan De Gendt; Robin Degraeve; Guido Groeseneken; Conny Kenens; D. Martin Knotter; Lee M. Loewenstein; Paul W. Mertens; Sofie Mertens; Marc Meuris; et al. (IBM J. Res. Dev., 1999)

Influence of gate length on ESD-performance for deep submicron CMOS technology. - Karlheinz Bock; Bart Keppens; Vincent De Heyn; Guido Groeseneken; L. Y. Ching; A. Naem (Microelectron. Reliab., 2001)

A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation. - R. Dreesen; Kris Croes; Jean Manca; Ward De Ceuninck; Luc De Schepper; A. Pergoot; Guido Groeseneken (Microelectron. Reliab., 2001)

Statistical aspects of the degradation of LDD nMOSFETs. - E. Andries; R. Dreesen; Kris Croes; Ward De Ceuninck; Luc De Schepper; Guido Groeseneken; K. F. Lo; Marc D'Olieslaeger; Jan D'Haen (Microelectron. Reliab., 2002)

Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study. - Ben Kaczer; Robin Degraeve; Mahmoud Rasras; An De Keersgieter; K. Van de Mieroop; Guido Groeseneken (Microelectron. Reliab., 2002)

Significance of the failure criterion on transmission line pulse testing. - Bart Keppens; Vincent De Heyn; M. Natarajan Iyer; Vesselin K. Vassilev; Guido Groeseneken (Microelectron. Reliab., 2002)

High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices. - Vesselin K. Vassilev; Snezana Jenei; Guido Groeseneken; Rafael Venegas; Steven Thijs; Vincent De Heyn; M. Natarajan Iyer; Michiel Steyaert; Herman E. Maes (Microelectron. Reliab., 2003)

Evidence for source side injection hot carrier effects on lateral DMOS transistors. - Stefano Aresu; Ward De Ceuninck; Geert Van den Bosch; Guido Groeseneken; Peter Moens; Jean Manca; D. Wojciechowski; P. Gassot (Microelectron. Reliab., 2004)

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits. - Vesselin K. Vassilev; Vladislav A. Vashchenko; Philippe Jansen; B.-J. Choi; Ann Concannon; J.-J. Yang; Guido Groeseneken; M. I. Natarajan; Marcel ter Beek; Peter Hopper; Michiel Steyaert; Herman E. Maes (Microelectron. Reliab., 2004)

RF ESD protection strategies - the design and performance trade-off challenges. - Philippe Jansen; Steven Thijs; Dimitri Linten; M. I. Natarajan; Vesselin K. Vassilev; Mingxu Liu; Ann Concannon; David Trémouilles; Takeshi Nakaie; Masanori Sawada; Vladislav A. Vashchenko; Marcel ter Beek; et al. (CICC, 2005)

Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability. - Yunlong Li; Zsolt Tökei; Philippe Roussel; Guido Groeseneken; Karen Maex (Microelectron. Reliab., 2005)

ESD-RF co-design methodology for the state of the art RF-CMOS blocks. - Vesselin K. Vassilev; Steven Thijs; P. L. Segura; Piet Wambacq; Paul Leroux; Guido Groeseneken; M. I. Natarajan; Herman E. Maes; Michiel Steyaert (Microelectron. Reliab., 2005)

ESD circuit model based protection network optimisation for extended-voltage NMOS drivers. - Vesselin K. Vassilev; Vladislav A. Vashchenko; Philippe Jansen; Guido Groeseneken; Marcel ter Beek (Microelectron. Reliab., 2005)

FinFET and MOSFET preliminary comparison of gate oxide reliability. - Raul Fernández; Rosana Rodríguez; Montserrat Nafría; Xavier Aymerich; Ben Kaczer; Guido Groeseneken (Microelectron. Reliab., 2006)

Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS LNAs - Concepts, constraints and solutions. - Steven Thijs; M. Natarajan Iyer; Dimitri Linten; Wutthinan Jeamsaksiri; T. Daenen; Robin Degraeve; Andries J. Scholten; Stefaan Decoutere; Guido Groeseneken (Microelectron. Reliab., 2006)

FinFET technology for analog and RF circuits. - Bertrand Parvais; Vaidyanathan Subramanian; Abdelkarim Mercha; Morin Dehan; Piet Wambacq; Willy Sansen; Guido Groeseneken; Stefaan Decoutere (ICECS, 2007)

Negative bias temperature instabilities in HfSiO(N)-based MOSFETs: Electrical characterization and modeling. - M. Houssa; Marc Aoulaiche; Stefan De Gendt; Guido Groeseneken; Marc M. Heyns (Microelectron. Reliab., 2007)

Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability. - Ben Kaczer; Robin Degraeve; Philippe Roussel; Guido Groeseneken (Microelectron. Reliab., 2007)

Reliability screening of high-k dielectrics based on voltage ramp stress. - A. Kerber; Luigi Pantisano; Anabela Veloso; Guido Groeseneken; Martin Kerber (Microelectron. Reliab., 2007)

NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase. - A. Shickova; Ben Kaczer; Anabela Veloso; Marc Aoulaiche; M. Houssa; Herman E. Maes; Guido Groeseneken; J. A. Kittl (Microelectron. Reliab., 2007)

Transient voltage overshoot in TLP testing - Real or artifact? - David Trémouilles; Steven Thijs; Philippe Roussel; M. I. Natarajan; Vesselin K. Vassilev; Guido Groeseneken (Microelectron. Reliab., 2007)

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. - Steven Thijs; Mototsugu Okushima; Jonathan Borremans; Philippe Jansen; Dimitri Linten; Mirko Scholz; Piet Wambacq; Guido Groeseneken (CICC, 2008)

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. - Georges G. E. Gielen; Pieter De Wit; Elie Maricau; Johan Loeckx; Javier Martín-Martínez; Ben Kaczer; Guido Groeseneken; Rosana Rodríguez; Montserrat Nafría (DATE, 2008)

Editorial. - Guido Groeseneken; Ingrid De Wolf; A. J. Mouthaan; Jaap Bisschop (Microelectron. Reliab., 2008)

A CMOS circuit for evaluating the NBTI over a wide frequency range. - R. Fernández-García; Ben Kaczer; Guido Groeseneken (Microelectron. Reliab., 2009)

A plug-and-play wideband RF circuit ESD protection methodology: T-diodes. - Dimitri Linten; Steven Thijs; Jonathan Borremans; Morin Dehan; David Trémouilles; Mirko Scholz; M. I. Natarajan; Piet Wambacq; Stefaan Decoutere; Guido Groeseneken (Microelectron. Reliab., 2009)

ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool? - Mirko Scholz; Dimitri Linten; Steven Thijs; Sandeep Sangameswaran; Masanori Sawada; Toshiyuki Nakaei; Takumi Hasebe; Guido Groeseneken (IEEE Trans. Instrum. Meas., 2009)

Identifying the Bottlenecks to the RF Performance of FinFETs. - Vaidyanathan Subramanian; Abdelkarim Mercha; Bertrand Parvais; Morin Dehan; Guido Groeseneken; Willy M. C. Sansen; Stefaan Decoutere (VLSI Design, 2010)

Impact of design factors and environment on the ESD sensitivity of MEMS micromirrors. - Sandeep Sangameswaran; Jeroen De Coster; Guido Groeseneken; Ingrid De Wolf (Microelectron. Reliab., 2010)

Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (ISCAS, 2011)

Positive bias temperature instabilities on sub-nanometer EOT FinFETs. - P. C. Feijoo; Moonju Cho; Mitsuhiro Togo; E. San Andrés; Guido Groeseneken (Microelectron. Reliab., 2011)

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model. - Halil Kukner; Pieter Weckx; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (DSD, 2012)

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. - Tommaso Romeo; Luigi Pantisano; Eddy Simoen; Raymond Krom; Mitsuhiro Togo; N. Horiguchi; Jérôme Mitard; Aaron Thean; Guido Groeseneken; Cor Claeys; Felice Crupi (ESSDERC, 2012)

Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write. - Leqi Zhang; Stefan Cosemans; Dirk J. Wouters; Guido Groeseneken; Malgorzata Jurczak (ESSDERC, 2012)

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. - Jacopo Franco; Ben Kaczer; Jérôme Mitard; Maria Toledano-Luque; Felice Crupi; Geert Eneman; Ph. J. Rousse; Tibor Grasser; M. Cho; Thomas Kauerauf; Liesbeth Witters; Geert Hellings; et al. (ICICDT, 2012)

BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic. - Jacopo Franco; S. Graziano; Ben Kaczer; Felice Crupi; Lars-Åke Ragnarsson; Tibor Grasser; Guido Groeseneken (Microelectron. Reliab., 2012)

Defect-centric perspective of time-dependent BTI variability. - Maria Toledano-Luque; Ben Kaczer; Jacopo Franco; Philippe Roussel; Tibor Grasser; Guido Groeseneken (Microelectron. Reliab., 2012)

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Mitsuhiro Togo; N. Horiguchi; Guido Groeseneken (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies. - Geert Hellings; Shih-Hung Chen; Dimitri Linten; Mirko Scholz; Guido Groeseneken (CICC, 2013)

Reliability challenges of real-time systems in forthcoming technology nodes. - Said Hamdioui; Michael Nicolaidis; Dimitris Gizopoulos; Arnaud Grasset; Guido Groeseneken; Philippe Bonnot 001 (DATE, 2013)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model. - Halil Kükner; Pieter Weckx; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (Microprocess. Microsystems, 2013)

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes. - Halil Kukner; Pieter Weckx; Sebastien Morrison; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (DSD, 2014)

Impact of etch stop layer on negative bias illumination stress of amorphous Indium Gallium Zinc Oxide transistors. - Ajay Bhoolokam; Manoj Nag; Adrian Vaisman Chasin; Soeren Steudel; Jan Genoe; Gerwin H. Gelinck; Guido Groeseneken; Paul Heremans (ESSDERC, 2014)

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology. - Halil Kukner; Moustafa A. Khatib; Sebastien Morrison; Pieter Weckx; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (ISQED, 2014)

Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures. - Chunmeng Dou; Dennis Lin; Abhitosh Vais; Tsvetan Ivanov; Han-Ping Chen; Koen Martens; Kuniyuki Kakushima; Hiroshi Iwai; Yuan Taur; Aaron Thean; Guido Groeseneken (Microelectron. Reliab., 2014)

Energy distribution of positive charges in high-k dielectric. - Sharifah Wan Muhamad Hatta; Zhigang Ji; Jianfu Zhang 001; Weidong Zhang 002; Norhayati Soin; Ben Kaczer; Stefan De Gendt; Guido Groeseneken (Microelectron. Reliab., 2014)

Physical origin of current collapse in Au-free AlGaN/GaN Schottky Barrier Diodes. - Jie Hu; Steve Stoffels; Silvia Lenci; Nicolo Ronchi; Rafael Venegas; Shuzhen You; Benoit Bakeroot; Guido Groeseneken; Stefaan Decoutere (Microelectron. Reliab., 2014)

Stability evaluation of Au-free Ohmic contacts on AlGaN/GaN HEMTs under a constant current stress. - Tian-Li Wu; Denis Marcon; Steve Stoffels; Shuzhen You; Brice De Jaeger; Marleen Van Hove; Guido Groeseneken; Stefaan Decoutere (Microelectron. Reliab., 2014)

Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits. - Vinicius V. A. Camargo; Ben Kaczer; Gilson I. Wirth; Tibor Grasser; Guido Groeseneken (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Characterization and simulation methodology for time-dependent variability in advanced technologies. - Pieter Weckx; Ben Kaczer; Praveen Raghavan; Jacopo Franco; Marko Simicic; Philippe J. Roussel; Dimitri Linten; Aaron Thean; Diederik Verkest; Francky Catthoor; Guido Groeseneken (CICC, 2015)

Engineering of a TiN Al2O3 (Hf, Al)O2 Ta2O5 Hf RRAM cell for fast operation at low current. - C. Y. Chen; Ludovic Goux; Andrea Fantini; Robin Degraeve; Augusto Redolfi; Guido Groeseneken; Malgorzata Jurczak (ESSDERC, 2015)

The defect-centric perspective of device and circuit reliability - From individual defects to circuits. - Ben Kaczer; Jacopo Franco; Pieter Weckx; Philippe Roussel; Erik Bury; Moonju Cho; Robin Degraeve; Dimitri Linten; Guido Groeseneken; Halil Kukner; Praveen Raghavan; Francky Catthoor; et al. (ESSDERC, 2015)

ESD protection diodes in optical interposer technology. - Roman Boschke; Guido Groeseneken; Mirko Scholz; Shih-Hung Chen; Geert Hellings; Peter Verheyen; Dimitri Linten (ICICDT, 2015)

Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology. - Pieter Weckx; Ben Kaczer; Philippe J. Roussel; Francky Catthoor; Guido Groeseneken (ICICDT, 2015)

Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions. - Simon Van Beek; Koen Martens; Philippe Roussel; Gabriele Luca Donadio; Johan Swerts; Sofie Mertens; Gouri Sankar Kar; Tai Min; Guido Groeseneken (IRPS, 2015)

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. - Jacopo Franco; Ben Kaczer; Philippe J. Roussel; Erik Bury; Hans Mertens; Romain Ritzenthaler; Tibor Grasser; Naoto Horiguchi; Aaron Thean; Guido Groeseneken (IRPS, 2015)

ESD characterization of planar InGaAs devices. - Zhigang Ji; Dimitri Linten; Roman Boschke; Geert Hellings; S. H. Chen; AliReza Alian; D. Zhou; Yves Mols; Tsvetan Ivanov; Jacopo Franco; Ben Kaczer; X. Zhang; et al. (IRPS, 2015)

Origins and implications of increased channel hot carrier variability in nFinFETs. - Ben Kaczer; Jacopo Franco; M. Cho; Tibor Grasser; Philippe J. Roussel; Stanislav Tyaginov; M. Bina; Yannick Wimmer; Luis-Miguel Procel; Lionel Trojman; Felice Crupi; Gregory Pitner; et al. (IRPS, 2015)

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices. - Abhitosh Vais; Koen Martens; Jacopo Franco; Dennis Lin; AliReza Alian; Philippe Roussel; S. Sioncke; Nadine Collaert; Aaron Thean; Marc M. Heyns; Guido Groeseneken; Kristin De Meyer (IRPS, 2015)

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology. - Pieter Weckx; Ben Kaczer; C. Chen; Jacopo Franco; Erik Bury; Kausik Chanda; J. Watt; Philippe J. Roussel; Francky Catthoor; Guido Groeseneken (IRPS, 2015)

Time dependent dielectric breakdown (TDDB) evaluation of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode MIS-HEMTs and E-mode MIS-FETs. - Tian-Li Wu; Denis Marcon; Brice De Jaeger; Marleen Van Hove; Benoit Bakeroot; Steve Stoffels; Guido Groeseneken; Stefaan Decoutere; Robin Roelofs (IRPS, 2015)

Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. - Halil Kükner; Pieter Weckx; Sébastien Morrison; Jacopo Franco; Maria Toledano-Luque; Moonju Cho; Praveen Raghavan; Ben Kaczer; Doyoung Jang; Kenichi Miyaguchi; Marie Garcia Bardon; Francky Catthoor; et al. (Microprocess. Microsystems, 2015)

Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors. - Devin Verreck; Anne S. Verhulst; Bart Soree; Nadine Collaert; Anda Mocuta; Aaron Thean; Guido Groeseneken (ESSDERC, 2016)

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures. - Yashwanth Balaji; Quentin Smets; Cesar J. Lockhart de la Rosa; Anh Khoa Augustin Lu; Daniele Chiappe; Tarun Agarwal; Dennis Lin; Cedric Huyghebaert; Iuliana P. Radu; Dan Mocuta; Guido Groeseneken (ESSDERC, 2017)

From planar to vertical capacitors: A step towards ferroelectric V-FeFET integration. - Karine Florent; Simone Lavizzari; Luca Di Piazza; Mihaela Ioana Popovici; Goedele Potoms; Tom Raymaekers; Guido Groeseneken; Jan Van Houdt (ESSDERC, 2017)

ESD characterisation of a-IGZO TFTs on Si and foil substrates. - Nian Wang 004; Shih-Hung Chen; Geert Hellings; Kris Myny; Soeren Steudel; Mirko Scholz; Roman Boschke; Dimitri Linten; Guido Groeseneken (ESSDERC, 2017)

Will Chips of the Future Learn How to Feel Pain and Cure Themselves? - Francky Catthoor; Guido Groeseneken (IEEE Des. Test, 2017)

Impact of calibrated band-tails on the subthreshold swing of pocketed TFETs. - Jasper Bizindavyi; Anne S. Verhulst; Bart Soree; Guido Groeseneken (DRC, 2018)

A multi-bit/cell PUF using analog breakdown positions in CMOS. - Kai-Hsin Chuang; Erik Bury; Robin Degraeve; Ben Kaczer; T. Kallstenius; Guido Groeseneken; Dimitri Linten; Ingrid Verbauwhede (IRPS, 2018)

Investigation of the endurance of FE-HfO2 devices by means of TDDB studies. - Karine Florent; A. Subirats; Simone Lavizzari; Robin Degraeve; Umberto Celano; Ben Kaczer; Luca Di Piazza; Mihaela Ioana Popovici; Guido Groeseneken; Jan Van Houdt (IRPS, 2018)

Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps. - Vamsi Putcha; Jacopo Franco; Abhitosh Vais; Ben Kaczer; S. Sioncke; Dimitri Linten; Guido Groeseneken (IRPS, 2018)

A Cautionary Note When Looking for a Truly Reconfigurable Resistive RAM PUF. - Kai-Hsin Chuang; Robin Degraeve; Andrea Fantini; Guido Groeseneken; Dimitri Linten; Ingrid Verbauwhede (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

Tunnel FETs using Phosphorene/ReS2 heterostructures. - Yashwanth Balaji; Quentin Smets; Dennis Lin; I. Asselberghs; Iuliana P. Radu; Guido Groeseneken (DRC, 2019)

Experimental calibration of the temperature dependence of the heterojunction bandgap in III-V tunneling devices. - Jasper Bizindavyi; Anne S. Verhulst; Quentin Smets; Bart Sorée; Guido Groeseneken (DRC, 2019)

Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors. - Shuzhen You; Xiangdong Li; Stefaan Decoutere; Guido Groeseneken; Zhanfei Chen; Jun Liu; Yuki Yamashita; Kazutoshi Kobayashi (ESSDERC, 2019)

Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs. - Michiel Vandemaele; Ben Kaczer; Stanislav Tyaginov; Zlatan Stanojevic; Alexander Makarov; Adrian Vaisman Chasin; Erik Bury; Hans Mertens; Dimitri Linten; Guido Groeseneken (IRPS, 2019)

Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling. - Zhicheng Wu; Jacopo Franco; Dieter Claes; Gerhard Rzepa; Philippe J. Roussel; Nadine Collaert; Guido Groeseneken; Dimitri Linten; Tibor Grasser; Ben Kaczer (IRPS, 2019)

The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation. - Michiel Vandemaele; Kai-Hsin Chuang; Erik Bury; Stanislav Tyaginov; Guido Groeseneken; Ben Kaczer (IRPS, 2020)

Understanding the memory window in 1T-FeFET memories: a depolarization field perspective. - K. Kaczmarek; Marie Garcia Bardon; Y. Xiang; Laurent Breuil; Nicolo Ronchi; Bertrand Parvais; Guido Groeseneken; Jan Van Houdt (IMW, 2021)

The properties, effect and extraction of localized defect profiles from degraded FET characteristics. - Michiel Vandemaele; Ben Kaczer; Stanislav Tyaginov; Jacopo Franco; Robin Degraeve; Adrian Vaisman Chasin; Zhicheng Wu; Erik Bury; Yang Xiang; Hans Mertens; Guido Groeseneken (IRPS, 2021)

Physics-based device aging modelling framework for accurate circuit reliability assessment. - Zhicheng Wu; Jacopo Franco; Brecht Truijen; Philippe Roussel; Stanislav Tyaginov; Michiel Vandemaele; Erik Bury; Guido Groeseneken; Dimitri Linten; Ben Kaczer (IRPS, 2021)

Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon. - Ping-Yi Hsieh; Artemisia Tsiara; Barry J. O'Sullivan; Didit Yudistira; Marina Baryshnikova; Guido Groeseneken; Bernardette Kunert; Marianna Pantouvaki; Joris Van Campenhout; Ingrid De Wolf (IRPS, 2022)

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs. - Michiel Vandemaele; Ben Kaczer; Stanislav Tyaginov; Erik Bury; Adrian Vaisman Chasin; Jacopo Franco; Alexander Makarov; Hans Mertens; Geert Hellings; Guido Groeseneken (IRPS, 2022)

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper. - Michiel Vandemaele; Ben Kaczer; Erik Bury; Jacopo Franco; Adrian Chasin; Alexander Makarov; Hans Mertens; Geert Hellings; Guido Groeseneken (IRPS, 2023)

Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs. - Wen-Chieh Chen; S.-H. Chen; Anabela Veloso; Kateryna Serbulova; Geert Hellings; Guido Groeseneken (VLSI Technology and Circuits, 2023)

Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications. - Kateryna Serbulova; Zi-En Qiu; Shih-Hung Chen; Alexander Grill; Kuo-Hsing Kao; Jo De Boeck; Guido Groeseneken (IRPS, 2024)

A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology. - Wen-Chieh Chen; Shih-Hung Chen; Man-Ching Huang; Shu-Wei Chang; Geert Hellings; Guido Groeseneken (IEEE J. Solid State Circuits, 2025)