Encoded 16-PSK: a study for the receiver design. - Sergio Benedetto; Marco Ajmone Marsan; Guido Masera; Gabriella Olmo; Z. Zhang (IEEE J. Sel. Areas Commun., 1989)

PROXIMA: PROlog eXecutIon MAchine. - Livio Baldi; Pierluigi Civera; Angela Iurlaro; Guido Masera; Andrea Pagni; Gianluca Piccinini; Rinaldo Poluzzi; Massimo Ruo Roch; Maurizio Zamboni (IEEE J. Solid State Circuits, 1993)

A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. - F. Fraternali; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (EUSIPCO, 1996)

A Parametrical Architecture for Reed-Solomon Decoders. - Mariana-Eugenia Petre; Guido Masera (Great Lakes Symposium on VLSI, 1996)

A 500 MHz 2d-DWT VLSI processor. - A. Brizio; Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (EUSIPCO, 1998)

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. - Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (Applied Informatics, 1999)

New 2 Gbit/s CMOS I/O pads. - Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (Great Lakes Symposium on VLSI, 1999)

A global optimization tool for CMOS logic circuits. - Marco Delaurenti; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (ICECS, 1999)

VLSI architectures for turbo codes. - Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A 50 Mbit/s Iterative Turbo-Decoder. - Fabrizio Viglione; Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (DATE, 2000)

A high accuracy-low complexity model for CMOS delays. - Mario Roberto Casu; Guido Masera; Gianluca Piccinini; Massimo Ruo Roch; Maurizio Zamboni (ISCAS, 2000)

Noise Safety Design Methodologies. - Mariagrazia Graziano; Marco Delaurenti; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (ISQED, 2000)

JPEG 2000: finite precision representation and hardware implications. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICECS, 2001)

Reconfigurable coprocessor based JPEG 2000 implementation. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICECS, 2001)

Synthesis of low-leakage PD-SOI circuits with body-biasing. - Mario R. Casu; Gianluca Piccinini; Guido Masera; Maurizio Zamboni (ISLPED, 2001)

Hierarchical power supply noise evaluation for early power grid design prediction. - Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (SLIP, 2001)

Switching Noise Analysis Framework For High Speed Logic Families. - Marco Delaurenti; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (VLSI Design, 2001)

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (FPL, 2002)

Reconfigurable DSP IP for multimedia applications. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICASSP, 2002)

System architecture for error-resilient, embedded JPEG2000 wireless delivery. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (DSP, 2002)

Embedded IWT evaluation in reconfigurable wireless sensor network. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Fabrizio Vacca; Maurizio Zamboni (ICECS, 2002)

Clock Distribution Network Optimization under Self-Heating and Timing Constraints. - Mario R. Casu; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; M. M. Prono; Maurizio Zamboni (PATMOS, 2002)

Architectural strategies for low-power VLSI turbo decoders. - Guido Masera; Marco Mazza; Gianluca Piccinini; Fabrizio Viglione; Maurizio Zamboni (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. - Federico Quaglio; Maurizio Martina; Fabrizio Vacca; Guido Masera; Andrea Molino; Gianluca Piccinini; Maurizio Zamboni (FPGA, 2003)

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. - M. Addino; Mario R. Casu; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (PATMOS, 2003)

Effects of Temperature in Deep-Submicron Global Interconnect Optimization. - Mario R. Casu; Mariagrazia Graziano; Gianluca Piccinini; Guido Masera; Maurizio Zamboni (PATMOS, 2003)

Coupled electro-thermal modeling and optimization of clock networks. - Mario R. Casu; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (Microelectron. J., 2003)

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. - Maurizio Martina; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (J. VLSI Signal Process., 2003)

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. - Paolo Bernardi; Guido Masera; Federico Quaglio; Matteo Sonza Reorda (DATE, 2004)

A statistical model for estimating the effect of process variations on crosstalk noise. - Maurizio Martina; Guido Masera (SLIP, 2004)

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. - Mariagrazia Graziano; Mario R. Casu; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (Microelectron. J., 2004)

An electromigration and thermal model of power wires for a priori high-level reliability prediction. - Mario R. Casu; Mariagrazia Graziano; Guido Masera; Gianluca Piccinini; Maurizio Zamboni (IEEE Trans. Very Large Scale Integr. Syst., 2004)

High Performance Channel Model Hardware Emulator for 802.11n. - Alberto Dassatti; Guido Masera; Mario Nicola; Andrea Concil; Angelo Poloni (FPT, 2005)

Low-complexity, efficient 9/7 wavelet filters implementation. - Maurizio Martina; Guido Masera (ICIP (3), 2005)

Optimized CORDIC core for frequency-domain motion estimation. - Andrea Molino; Fabrizio Vacca; Guido Masera (ICIP (3), 2005)

Design and implementation of phase correlation based motion estimator. - Andrea Molino; Fabrizio Vacca; Guido Masera (SoCC, 2005)

A new approach to compress the configuration information of programmable devices. - Maurizio Martina; Guido Masera; Andrea Molino; Fabrizio Vacca; Luca Sterpone; Massimo Violante (DATE Designers' Forum, 2006)

Interconnection framework for high-throughput, flexible LDPC decoders. - Federico Quaglio; Fabrizio Vacca; Cristiano Castellano; Alberto Tarable; Guido Masera (DATE Designers' Forum, 2006)

Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding. - Maurizio Martina; Guido Masera; Luca Fanucci; Sergio Saponara (EUSIPCO, 2006)

Design of Application Specific Processors for the Cached FFT Algorithm. - Oguzhan Atak; Abdullah Atalar; Erdal Arikan; Harold Ishebabi; David Kammler; Gerd Ascheid; Heinrich Meyr; Mario Nicola; Guido Masera (ICASSP (3), 2006)

A VLSI Decoder for the Golden code. - Barbara Cerato; Guido Masera; Emanuele Viterbo (ICECS, 2006)

Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information. - Giorgio Pioppo; Rashid Ansari; Ashfaq A. Khokhar; Guido Masera (ICIP, 2006)

Error correcting arithmetic coding for JPEG 2000: memory and performance analysis. - Simone Zezza; Marco Grangetto; Maurizio Martina; Fabrizio Vacca; Guido Masera (MobiMedia, 2006)

Mixed hardware-software testbed for IEEE-802.11n. - Mario Nicola; Alberto Dassatti; Guido Masera; Andrea Concil; Angelo Poloni (TRIDENTCOM, 2006)

Mumford and Shah Functional: VLSI Analysis and Implementation. - Maurizio Martina; Guido Masera (IEEE Trans. Pattern Anal. Mach. Intell., 2006)

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Hardware architecture for matrix factorization in mimo receivers. - Barbara Cerato; Guido Masera; Peter Nilsson 001 (ACM Great Lakes Symposium on VLSI, 2007)

Beyond 3G wireless communication system prototype. - Alberto Dassatti; Simone Zezza; Mario Nicola; Guido Masera (ACM Great Lakes Symposium on VLSI, 2007)

Flexible blocks for high throughput serially concatenated convolutional codes. - Maurizio Martina; Guido Masera (ACM Great Lakes Symposium on VLSI, 2007)

Real-time implementation of a time-frequency analysis scheme. - Maurizio Martina; Andrea Terreno; Fabrizio Vacca; Andrea Molino; Guido Masera; Giuseppe D'Angelo; Giorgio Pasquettaz (ACM Great Lakes Symposium on VLSI, 2007)

Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Implementation of a Flexible LDPC Decoder. - Guido Masera; Federico Quaglio; Fabrizio Vacca (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

VLSI implementation of SISO arithmetic decoders for joint source channel coding. - Simone Zezza; Guido Masera (DATE, 2008)

Error resilient JPEG2000 decoding for wireless applications. - Simone Zezza; Maurizio Martina; Guido Masera; Saeid Nooshabadi (ICIP, 2008)

Decoding the golden space-time trellis coded modulation. - Barbara Cerato; Guido Masera; Emanuele Viterbo (IEEE Commun. Lett., 2008)

Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding. - Maurizio Martina; Mario Nicola; Guido Masera (IEEE Commun. Lett., 2008)

Design of a VLSI Decoder for Partially Structured LDPC Codes. - Fabrizio Vacca; Libero Dinoi; Guido Masera (Int. J. Digit. Multim. Broadcast., 2008)

Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Flexible UMTS-WiMax Turbo Decoder Architecture. - Maurizio Martina; Mario Nicola; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Enabling VLSI Processing Blocks for MIMO-OFDM Communications. - Barbara Cerato; Guido Masera; Emanuele Viterbo (VLSI Design, 2008)

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. - Fabrizio Vacca; Guido Masera; Hazem Moussa; Amer Baghdadi; Michel Jézéquel (DSD, 2009)

A feasible VLSI engine for soft-input-soft-output for joint source channel codes. - Simone Zezza; Guido Masera; Saeid Nooshabadi (ICIP, 2009)

Look-Ahead Sphere Decoding: Algorithm and performance evaluation. - Micaela Troglia Gamba; Guido Masera (ISWCS, 2009)

On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator. - Stylianos Papaharalabos; P. Takis Mathiopoulos; Guido Masera; Maurizio Martina (IEEE Commun. Lett., 2009)

A new performance evaluation metric for sub-optimal iterative decoders. - Ashwani Singh; Ali Al Ghouwayel; Guido Masera; Emmanuel Boutillon (IEEE Commun. Lett., 2009)

Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder. - Maurizio Martina; Mario Nicola; Guido Masera (J. Circuits Syst. Comput., 2009)

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring. - Andrea Molino; Maurizio Martina; Fabrizio Vacca; Guido Masera; Andrea Terreno; Giorgio Pasquettaz; Giuseppe D'Angelo (Microprocess. Microsystems, 2009)

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000. - Simone Zezza; Saeid Nooshabadi; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. Video Technol., 2009)

Decoding the Golden Code: A VLSI Design. - Barbara Cerato; Guido Masera; Emanuele Viterbo (IEEE Trans. Very Large Scale Integr. Syst., 2009)

ALOE-Based Flexible LDPC Decoder. - Ismael Gómez; Massimo Camatel; Jordi Bracke; Vuk Marojevic; Antoni Gelonch; Fabrizio Vacca; Guido Masera (DSD, 2010)

A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. - Bin Wu; Guido Masera (DSD, 2010)

Thermal Control for Crossbar-Based Input-Queued Switches. - Andrea Bianco; Paolo Giaccone; Guido Masera; Marco Ricca (GLOBECOM, 2010)

VLSI Architectures for WIMAX Channel Decoders - Maurizio Martina; Guido Masera (CoRR, 2010)

Scalable low-complexity B-spline discrete wavelet transform architecture. - Maurizio Martina; Guido Masera; Gianluca Piccinini (IET Circuits Devices Syst., 2010)

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding. - Sergio Saponara; Maurizio Martina; Michele Casula; Luca Fanucci; Guido Masera (Microprocess. Microsystems, 2010)

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications. - Muhammad Awais 004; Ashwani Singh; Guido Masera (ACC (2), 2011)

A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods. - Carlo Condo; Guido Masera (DASIP, 2011)

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder. - Muhammad Awais 004; Ashwani Singh; Emmanuel Boutillon; Guido Masera (DSD, 2011)

A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture - Carlo Condo; Guido Masera (CoRR, 2011)

Multiplierless Mumford and Shah Functional Implementation. - Maurizio Martina; Guido Masera (Circuits Syst. Signal Process., 2011)

Look-ahead sphere decoding: algorithm and VLSI architecture. - Micaela Troglia Gamba; Guido Masera (IET Commun., 2011)

On chip interconnects for multiprocessor turbo decoding architectures. - Maurizio Martina; Guido Masera; Hazem Moussa; Amer Baghdadi (Microprocess. Microsystems, 2011)

State Metric Compression Techniques for Turbo Decoder Architectures. - Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A Network-on-Chip-based turbo/LDPC decoder architecture. - Carlo Condo; Maurizio Martina; Guido Masera (DATE, 2012)

FFT implementation using QCA. - Muhammad Awais 004; Marco Vacca; Mariagrazia Graziano; Guido Masera (ICECS, 2012)

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation. - Lorenzo Guerrieri; Paola Bisaglia; Maurizio Martina; Guido Masera (ISTC, 2012)

Non-recursive max* operator with reduced implementation complexity for turbo decoding. - Stylianos Papaharalabos; Panayiotis Takis Mathiopoulos; Guido Masera; Maurizio Martina (IET Commun., 2012)

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder. - Bin Wu; Guido Masera (IET Commun., 2012)

An application specific instruction set processor based implementation for signal detection in multiple antenna systems. - M. Tamagnone; Maurizio Martina; Guido Masera (Microprocess. Microsystems, 2012)

An LDPC Decoder Architecture for Wireless Sensor Network Applications. - Andrea Dario Giancarlo Biroli; Maurizio Martina; Guido Masera (Sensors, 2012)

On Practical Implementation and Generalizations of max* Operator for Turbo and LDPC Decoders. - Maurizio Martina; Guido Masera; Stylianos Papaharalabos; P. Takis Mathiopoulos; Fotios Gioulekas (IEEE Trans. Instrum. Meas., 2012)

High Speed Architectures for Finding the First two Maximum/Minimum Values. - Luca Gaetano Amarù; Maurizio Martina; Guido Masera (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. - Christina Gimmler-Dumont; Frank Kienle; Bin Wu; Guido Masera (VLSI Design, 2012)

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. - Guido Masera; Amer Baghdadi; Frank Kienle; Christophe Moy (VLSI Design, 2012)

FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories. - Syed Azhar Ali Zaidi; Muhammad Awais 004; Carlo Condo; Maurizio Martina; Guido Masera (DASIP, 2013)

VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding. - Ashfaq Ahmed; Muhammad Usman Shahid; Maurizio Martina; Enrico Magli; Guido Masera (DSD, 2013)

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. - Carlo Condo; Amer Baghdadi; Guido Masera (DSD, 2013)

Analysis on parallel implementations of fixed-complexity sphere decoder. - Bin Wu; Guido Masera (Sci. China Inf. Sci., 2013)

Power Control for Crossbar-Based Input-Queued Switches. - Andrea Bianco; Paolo Giaccone; Guido Masera; Marco Ricca (IEEE Trans. Computers, 2013)

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture. - Carlo Condo; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes. - Simone Zezza; Saeid Nooshabadi; Guido Masera (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Improving Network-on-Chip-based Turbo Decoder Architectures. - Maurizio Martina; Guido Masera (J. Signal Process. Syst., 2013)

A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic. - Simone Zezza; Guido Masera; Saeid Nooshabadi (ISCAS, 2014)

Molecular transistor circuits: From device model to circuit simulation. - Ali Zahir; Syed Azhar Ali Zaidi; Azzurra Pulimeno; Mariagrazia Graziano; Danilo Demarchi; Guido Masera; Gianluca Piccinini (NANOARCH, 2014)

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications. - Carlo Condo; Maurizio Martina; Massimo Ruo Roch; Guido Masera (PDP, 2014)

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. - Maurizio Martina; Carlo Condo; Guido Masera; Maurizio Zamboni (IEEE Embed. Syst. Lett., 2014)

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. - Carlo Condo; Amer Baghdadi; Guido Masera (IET Commun., 2014)

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. - Carlo Condo; Maurizio Martina; Gianluca Piccinini; Guido Masera (IEEE Signal Process. Lett., 2014)

Unified turbo/LDPC code decoder architecture for deep-space communications. - Carlo Condo; Guido Masera (IEEE Trans. Aerosp. Electron. Syst., 2014)

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. - Guoping Xiao; Maurizio Martina; Guido Masera; Gianluca Piccinini (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures. - Maurizio Martina; Stylianos Papaharalabos; P. Takis Mathiopoulos; Guido Masera (IEEE Trans. Instrum. Meas., 2014)

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation. - Maurizio Awais; Guido Masera; Maurizio Martina; Guido Montorsi (IEEE Trans. Signal Process., 2014)

Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. - Maurizio Masera; Lorenzo Re Fiorentin; Maurizio Martina; Guido Masera; Enrico Masala (DASIP, 2015)

An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission. - Masoud Shahshahani Amirhossein; Paolo Motto Ros; Alberto Bonanno; Marco Crepaldi; Maurizio Martina; Danilo Demarchi; Guido Masera (DATE, 2015)

Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding. - Waqar Ahmad; Maurizio Martina; Guido Masera (IC3D, 2015)

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. - Carlo Condo; Amer Baghdadi; Guido Masera (Circuits Syst. Signal Process., 2015)

Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations". - Stylianos Papaharalabos; P. Takis Mathiopoulos; Maurizio Martina; Guido Masera (IEEE Commun. Lett., 2015)

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures. - Carlo Condo; Maurizio Martina; Massimo Ruo Roch; Guido Masera (Integr., 2015)

Unequal Error Protection of Memories in LDPC Decoders. - Carlo Condo; Guido Masera; Paolo Montuschi (IEEE Trans. Computers, 2015)

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. - Maurizio Martina; Guido Masera; Massimo Ruo Roch; Gianluca Piccinini (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware. - Muhammad Usman Shahid; Ashfaq Ahmed; Maurizio Martina; Guido Masera; Enrico Magli (IEEE Trans. Circuits Syst. Video Technol., 2015)

High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters. - Waqar Ahmad; Javed Iqbal; Maurizio Martina; Guido Masera (EMS, 2016)

Comparison between HEVC and Thor based on objective and subjective assessments. - Lorenzo Re Fiorentin; Maurizio Masera; Sabino Mantovano; Paola Sunna; Guido Masera; Maurizio Martina (IWSSIP, 2016)

FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories. - Syed Azhar Ali Zaidi; Abuduwaili Tuoheti; Maurizio Martina; Guido Masera (IEEE Des. Test, 2016)

Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator. - Lorenzo Guerrieri; Guido Masera; Igor S. Stievano; Paola Bisaglia; Williams Richard Garcia Valverde; Mara Concolato (IEEE Trans. Ind. Electron., 2016)

A low power architecture for AER event-processing microcontroller. - Simone Aiassa; Paolo Motto Ros; Guido Masera; Maurizio Martina (BioCAS, 2017)

Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network. - Erik Anzalone; Maurizio Capra; Riccardo Peloso; Maurizio Martina; Guido Masera (IIH-MSP (1), 2017)

Approximate Arai DCT Architecture for HEVC. - Giovanni Renda; Maurizio Masera; Maurizio Martina; Guido Masera (NGCAS, 2017)

Odd type DCT/DST for video coding: Relationships and low-complexity implementations. - Maurizio Masera; Maurizio Martina; Guido Masera (SiPS, 2017)

Analysis of HEVC transform throughput requirements for hardware implementations. - Maurizio Masera; Lorenzo Re Fiorentin; Enrico Masala; Guido Masera; Maurizio Martina (Signal Process. Image Commun., 2017)

Adaptive Approximated DCT Architectures for HEVC. - Maurizio Masera; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. Video Technol., 2017)

An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. - Paolo Selvo; Maurizio Masera; Riccardo Peloso; Guido Masera; Muhammad Shafique 001; Maurizio Martina (ApplePies, 2018)

Approximate-Computing Architectures for Motion Estimation in HEVC. - Alberto Paltrinieri; Riccardo Peloso; Guido Masera; Muhammad Shafique 001; Maurizio Martina (NGCAS, 2018)

Efficient Operation Scheduling in Successive-Cancellation-based polar decoders. - Gabriele Coppolino; Carlo Condo; Guido Masera; Warren J. Gross (SiPS, 2018)

A Multi-Kernel Multi-Code Polar Decoder Architecture. - Gabriele Coppolino; Carlo Condo; Guido Masera; Warren J. Gross (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT). - Luigi Sole; Riccardo Peloso; Maurizio Capra; Massimo Ruo Roch; Guido Masera; Maurizio Martina (ApplePies, 2019)

X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations. - Alberto Marchisio; Beatrice Bussolino; Alessio Colucci; Muhammad Abdullah Hanif; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CoRR, 2019)

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World. - Maurizio Capra; Riccardo Peloso; Guido Masera; Massimo Ruo Roch; Maurizio Martina (Future Internet, 2019)

LDPC check node implementation using reversible logic. - Muhammad Awais 004; Anas Razzaq; Ashfaq Ahmed; Guido Masera (IET Circuits Devices Syst., 2019)

On the Effect of Approximate-Computing in Motion Estimation. - Alberto Paltrinieri; Riccardo Peloso; Guido Masera; Muhammad Shafique 001; Maurizio Martina (J. Low Power Electron., 2019)

A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. - Alessio Colucci; Alberto Marchisio; Beatrice Bussolino; Vojtech Mrazek; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CODES+ISSS, 2020)

Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. - Alberto Marchisio; Beatrice Bussolino; Alessio Colucci; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (DAC, 2020)

FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. - Alberto Marchisio; Beatrice Bussolino; Alessio Colucci; Muhammad Abdullah Hanif; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2020)

A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography. - Kristjane Koleci; Marco Baldi; Maurizio Martina; Guido Masera (ITASEC, 2020)

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. - Maurizio Capra; Beatrice Bussolino; Alberto Marchisio; Guido Masera; Maurizio Martina; Muhammad Shafique 001 (IEEE Access, 2020)

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. - Maurizio Capra; Beatrice Bussolino; Alberto Marchisio; Muhammad Shafique 001; Guido Masera; Maurizio Martina (Future Internet, 2020)

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. - Riccardo Peloso; Maurizio Capra; Luigi Sole; Massimo Ruo Roch; Guido Masera; Maurizio Martina (Sensors, 2020)

Low-Complexity Reconfigurable DCT-V Architecture. - Jurgen Kello; Massimo Ruo Roch; Guido Masera; Maurizio Martina (IEEE Trans. Circuits Syst., 2020)

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding. - Maurizio Masera; Guido Masera; Maurizio Martina (IEEE Trans. Circuits Syst. Video Technol., 2020)

DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. - Alberto Marchisio; Giacomo Pira; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2021)

CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. - Alberto Viale; Alberto Marchisio; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2021)

R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. - Alberto Marchisio; Giacomo Pira; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IROS, 2021)

Efficient Hardware Implementation of the LEDAcrypt Decoder. - Kristjane Koleci; Paolo Santini; Marco Baldi; Franco Chiaraluce; Maurizio Martina; Guido Masera (IEEE Access, 2021)

Real-time implementation of fast discriminative scale space tracking algorithm. - Walid Walid; Muhammad Awais 004; Ashfaq Ahmed; Guido Masera; Maurizio Martina (J. Real Time Image Process., 2021)

A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography. - Kristjane Koleci; Lorenzo Cecchetti; Guido Masera; Maurizio Martina; Massimo Ruo Roch (ApplePies, 2022)

NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators. - Giuseppe Aiello; Beatrice Bussolino; Emanuele Valpreda; Massimo Ruo Roch; Guido Masera; Maurizio Martina; Stefano Marsi (ICIP, 2022)

CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. - Muhammad Abdullah Hanif; Giuseppe Maria Sarda; Alberto Marchisio; Guido Masera; Maurizio Martina; Muhammad Shafique 001 (IJCNN, 2022)

LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. - Alberto Viale; Alberto Marchisio; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IROS, 2022)

Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. - Alberto Marchisio; Beatrice Bussolino; Edoardo Salvati; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (ISLPED, 2022)

LOKI Low-Latency Open-Source Kyber-Accelerator IPs. - Alessandra Dolmeta; Mattia Mirigaldi; Maurizio Martina; Guido Masera (ApplePies, 2023)

TEMET: Truncated REconfigurable Multiplier with Error Tuning. - Flavia Guella; Emanuele Valpreda; Michele Caon; Guido Masera; Maurizio Martina (ApplePies, 2023)

Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber. - Alessandra Dolmeta; Mattia Mirigaldi; Maurizio Martina; Guido Masera (CF, 2023)

SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. - Alberto Marchisio; Davide Dura; Maurizio Capra; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (IJCNN, 2023)

Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (PRIME, 2023)

ERODE: Error Resilient Object DetEction by Recovering Bounding Box and Class Information. - Emanuele Valpreda; Giuseppe Palumbo; Michele Caon; Guido Masera; Maurizio Martina (PRIME, 2023)

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. - William Fornaciari; Federico Reghenzani; Giovanni Agosta; Davide Zoni; Andrea Galimberti; Francesco Conti 001; Yvan Tortorella; Emanuele Parisi; Francesco Barchi; Andrea Bartolini; Andrea Acquaviva; Daniele Gregori; et al. (SAMOS, 2023)

A Flexible NTT-Based Multiplier for Post-Quantum Cryptography. - Kristjane Koleci; Paolo Mazzetti; Maurizio Martina; Guido Masera (IEEE Access, 2023)

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories. - Fabrizio Ottati; Giovanna Turvani; Marco Vacca; Guido Masera (CoRR, 2023)

Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders. - Simone Favero; Maurizio Martina; Guido Masera (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Comparative Study of Keccak SHA-3 Implementations. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (Cryptogr., 2023)

Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (ApplePies, 2024)

Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack. - Mattia Mirigaldi; Maurizio Martina; Guido Masera (ApplePies, 2024)

Seeing Beyond the Order: a LEN5 to Sharpen Edge Microprocessors with Dynamic Scheduling. - Michele Caon; Vincenzo Petrolo; Mattia Mirigaldi; Flavia Guella; Guido Masera; Maurizio Martina (CF (Companion), 2024)

Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber. - Alessandra Dolmeta; Emanuele Valpreda; Maurizio Martina; Guido Masera (CF (Companion), 2024)

ATHOS: A Hybrid Accelerator for PQC CRYSTALS-Algorithms Exploiting New CV-X-IF Interface. - Alessandra Dolmeta; Maurizio Martina; Guido Masera (IEEE Access, 2024)

TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems. - Eugenio Ressa; Alberto Marchisio; Maurizio Martina; Guido Masera; Muhammad Shafique 001 (CoRR, 2024)

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. - Michele Caon; Clément Choné; Pasquale Davide Schiavone; Alexandre Levisse; Guido Masera; Maurizio Martina; David Atienza (CoRR, 2024)

MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge. - Flavia Guella; Emanuele Valpreda; Michele Caon; Guido Masera; Maurizio Martina (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Stop Wasting your Cache! Bringing Machine Learning into Cache Computing. - Vincenzo Petrolo; Flavia Guella; Michele Caon; Guido Masera; Maurizio Martina (CF (Companion), 2025)

A Deep Dive into Integration Methodologies in RISC-V. - Valeria Piscopo; Alessandra Dolmeta; Mattia Mirigaldi; Maurizio Martina; Guido Masera (CF (Companion), 2025)

Just TestIt! An SBST Approach To Automate System-Integration Testing. - Tommaso Terzano; Luigi Giuffrida; Juan Sapriza; Pasquale Davide Schiavone; Guido Masera; David Atienza; Luciano Lavagno; Maurizio Martina (CF (Companion), 2025)

TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography. - Alessandra Dolmeta; Stefano Di Matteo; Emanuele Valea; Mikael Carmona; Antoine Loiseau; Maurizio Martina; Guido Masera (DATE, 2025)

RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards. - Alessandra Dolmeta; Valeria Piscopo; Mattia Mirigaldi; Maurizio Martina; Guido Masera (ISCAS, 2025)

CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON. - Alessandra Dolmeta; Valeria Piscopo; Maurizio Martina; Guido Masera (ISVLSI, 2025)

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions. - Vincenzo Petrolo; Flavia Guella; Michele Caon; Pasquale Davide Schiavone; Guido Masera; Maurizio Martina (CoRR, 2025)