Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec. - Kaifei Chen; Jiebin Niu; Guanhua Yang; Menggan Liu; Wendong Lu; Fuxi Liao; Kailiang Huang; Xinlv Duan; Congyan Lu; Jiawei Wang; Lingfei Wang; Mengmeng Li; et al. (VLSI Technology and Circuits, 2022)

Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement. - Z. Asher Bai; Yixian Wang; Lixue Liu; Xi Zhang; Feng Yuan; Junsheng Meng; Zhongming Liu; Js Jeon; James Cho; Blacksmith Wu; Huihui Li; Guilei Wang; et al. (IMW, 2023)

A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation. - Meng Huang; Shufang Si; Zheng He; Ying Zhou; Sijia Li; Hong Wang; Jinying Liu; Dongsheng Xie; Mengmeng Yang; Kang You; Chris Choi; Yi Tang; et al. (IMW, 2023)

Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM. - Wenqi Wang; Sang Don Yi; Fu Li; Qingchen Cao; Jiangliu Shi; Bok-Moon Kang; Meichen Jin; Chang Liu; Zhenhua Wu; Guilei Wang; Chao Zhao (IEEE Access, 2024)

Trap Behaviors and Degradation Modeling in Positive Bias Temperature Instability of Back Gated IGZO Transistors. - Liang Xiang; Gangping Yan; Yunfei Shi; Hong Yang; Shangbo Yang; Gaobo Xu; Xiaolei Wang; Guilei Wang; Huaxiang Yin; Chao Zhao; Jun Luo; Wenwu Wang 006 (IRPS, 2025)