Low noise and low cost neural amplifiers. - Guilherme Bontorin; Jean Tomas; Sylvie Renaud (ICECS, 2007)

A real-time setup for multisite signal recording and processing in living neural networks. - Guilherme Bontorin; Colin Lopez; Yannick Bornat; Noëlle Lewis; Sylvie Renaud; Mathieu C. Garenne; Gwendal Le Masson (ISCAS, 2008)

A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage. - Marco Terres; Cristina Meinhardt; Guilherme Bontorin; Ricardo Reis 001 (ICECS, 2013)

Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs. - Marco Terres; Cristina Meinhardt; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2014)

Low Latency FPGA Implementation of Izhikevich-Neuron Model. - Vitor V. Bandeira; Vivianne L. Costa; Guilherme Bontorin; Ricardo A. L. Reis (IESS, 2015)

Overhead for independent net approach for Global Routing. - Diego Tumelero; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2015)

Energy-efficient Level Shifter topology. - Roger Caputo-Llanos; Diego Sousa; Marco Terres; Guilherme Bontorin; Ricardo Reis 001; Marcelo O. Johann (PATMOS, 2015)

DHyANA: A NoC-based neural network hardware architecture. - Priscila C. Holanda; Cezar R. W. Reinbrecht; Guilherme Bontorin; Vitor V. Bandeira; Ricardo A. L. Reis (ICECS, 2016)

A nonlinear placement for FPGAs: The chaotic place. - Elias de Almeida Ramos; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2018)

Reducing the amount of transistors by gate merging. - Luciana Mendes da Silva; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2018)

A New Nonlinear Global Placement for FPGAs: The Chaotic Place. - Elias de Almeida Ramos; Guilherme Bontorin; Ricardo Reis 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)