Conclusively verifying clock-domain crossings in very large hardware designs. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Fahim Rahim; Shaker Sarwary; Dominique Borrione (VLSI-SoC, 2016)

Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Shaker Sarwary; Dominique Borrione (VLSI-SoC (Selected Papers), 2016)

Extraction of missing formal assumptions in under-constrained designs. - Guillaume Plassan; Katell Morin-Allory; Dominique Borrione (MEMOCODE, 2017)

Conclusive formal verification of clock domain crossing properties. (Vérification formelle concluante des propriétés des systèmes multi-horloges). - Guillaume Plassan (2018)

Mining Missing Assumptions from Counter-Examples. - Guillaume Plassan; Katell Morin-Allory; Dominique Borrione (ACM Trans. Embed. Comput. Syst., 2019)