A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. - Luís Rolíndez; Salvador Mir; Guillaume Prenat; Ahcène Bounceur (DATE, 2004)

A built-in IDDQ testing circuit. - Sotirios Matakias; Yiorgos Tsiatouhas; Angela Arapoyanni; Th. Haniotakis; Guillaume Prenat; Salvador Mir (ESSCIRC, 2005)

A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. - Guillaume Prenat; Salvador Mir; Diego Vázquez; Luís Rolíndez (Microelectron. J., 2005)

TAS-MRAM based Non-volatile FPGA logic circuit. - Weisheng Zhao; Eric Belhaire; Bernard Dieny; Guillaume Prenat; Claude Chappert (FPT, 2007)

CMOS/Magnetic Hybrid Architectures. - Guillaume Prenat; Mourad El Baraji; Wei Guo; Ricardo Sousa; Liliana Buda-Prejbeanu; Bernard Dieny; Virgile Javerliac; Jean-Pierre Nozieres; Weisheng Zhao; Eric Belhaire (ICECS, 2007)

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Bernard Dieny; Guillaume Prenat (ACM Trans. Reconfigurable Technol. Syst., 2009)

Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits. - Guillaume Prenat; Bernard Dieny; Jean-Pierre Nozieres; Gregory di Pendina; Kholdoun Torki (ICCAD, 2011)

Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. - Gregory di Pendina; Kholdoun Torki; Guillaume Prenat; Yoann Guillemenet; Lionel Torres (PATMOS, 2011)

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Guillaume Prenat; Jérémy Alvarez-Herault; Ken Mackay (Asian Test Symposium, 2012)

Impact of resistive-open defects on the heat current of TAS-MRAM architectures. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri-Sanial; Guillaume Prenat; Jérémy Alvarez-Herault; Ken Mackay (DATE, 2012)

Coupling-based resistive-open defects in TAS-MRAM architectures. - Joao Azevedo; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Guillaume Prenat; Jérémy Alvarez-Herault; Ken Mackay (ETS, 2012)

Non-volatile FPGAs based on spintronic devices. - Olivier Goncalves; Guillaume Prenat; Gregory di Pendina; Bernard Dieny (DAC, 2013)

Emerging hybrid logic circuits based on non-volatile magnetic memories. - Weisheng Zhao; Guillaume Prenat; Jacques-Olivier Klein; Bernard Dieny; Claude Chappert; Dafine Ravelosona (NEWCAS, 2013)

Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures. - Gregory di Pendina; Kotb Jabeur; Guillaume Prenat (ASP-DAC, 2014)

Magnetic memories: From DRAM replacement to ultra low power logic chips. - Guillaume Prenat; Gregory di Pendina; Christophe Layer; Olivier Goncalves; K. Jaber; Bernard Dieny; Ricardo C. Sousa; Ioan Lucian Prejbeanu; Jean-Pierre Nozieres (DATE, 2014)

InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers. - Gregory di Pendina; Guillaume Prenat; Bernard Dieny (EWME, 2014)

Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. - Erya Deng; You Wang 002; Zhaohao Wang; Jacques-Olivier Klein; Bernard Dieny; Guillaume Prenat; Weisheng Zhao (NANOARCH, 2015)

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. - Erya Deng; Yue Zhang 010; Wang Kang 001; Bernard Dieny; Jacques-Olivier Klein; Guillaume Prenat; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Multi-context non-volatile content addressable memory using magnetic tunnel junctions. - Erya Deng; Lorena Anghel; Guillaume Prenat; Weisheng Zhao (NANOARCH, 2016)

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories. - Christophe Layer; Laurent Becker; Kotb Jabeur; Sylvain Claireux; Bernard Dieny; Guillaume Prenat; Gregory di Pendina; Stephane Gros; Pierre Paoli; Virgile Javerliac; Fabrice Bernard-Granger; Loïc Decloedt (ACM J. Emerg. Technol. Comput. Syst., 2016)

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. - Guillaume Prenat; Kotb Jabeur; Pierre Vanhauwaert; Gregory di Pendina; Fabian Oboril; Rajendra Bishnoi; Mojtaba Ebrahimi; Nathalie Lamard; Olivier Boulle; Kevin Garello; Juergen Langer; Berthold Ocker; et al. (IEEE Trans. Multi Scale Comput. Syst., 2016)

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Sophiane Senni; Jad Mohdad; Frédérick Mailly; Lionel Torres; Pascal Benoit; Pascal Nouet; Rui Ma; Martin Kreißig; Frank Ellinger; et al. (ISVLSI, 2017)

Using multifunctional standardized stack as universal spintronic technology for IoT. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Sophiane Senni; Jad Mohdad; Frédérick Mailly; Lionel Torres; Pascal Benoit; Abdoulaye Gamatié; Pascal Nouet; Frederic Ouattara; Gilles Sassatelli; et al. (DATE, 2018)

MRAM: from STT to SOT, for security and memory. - Mounia Kharbouche-Harrari; Rana Alhalabi; Jérémy Postel-Pellerin; Romain Wacquez; Driss Aboulkassimi; Etienne Nowak; Ioan Lucian Prejbeanu; Guillaume Prenat; Gregory di Pendina (DCIS, 2018)

Resistive and Spintronic RAMs: Device, Simulation, and Applications. - Elena-Ioana Vatajelu; Lorena Anghel; Jean-Michel Portal; Marc Bocquet; Guillaume Prenat (IOLTS, 2018)

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip. - Sophiane Senni; Frederic Ouattara; Jad Mohdad; Kaan Sevin; Guillaume Patrigeon; Pascal Benoit; Pascal Nouet; Lionel Torres; François Duhem; Gregory di Pendina; Guillaume Prenat (VLSI-SoC, 2018)

Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers. - Guillaume Patrigeon; Pascal Benoit; Lionel Torres; Sophiane Senni; Guillaume Prenat; Gregory di Pendina (IEEE Access, 2019)

A Universal Spintronic Technology based on Multifunctional Standardized Stack. - Mehdi Baradaran Tahoori; Sarath Mohanachandran Nair; Rajendra Bishnoi; Lionel Torres; Sophiane Senni; Guillaume Patrigeon; Pascal Benoit; Gregory di Pendina; Guillaume Prenat (DATE, 2020)

Fast Behavioral VerilogA Compact Model for Stochastic MTJ. - Etienne Becle; Philippe Talatchian; Guillaume Prenat; Lorena Anghel; Ioan Lucian Prejbeanu (ESSDERC, 2021)

Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. - Kamal Danouchi; Guillaume Prenat; Lorena Anghel (LATS, 2022)

Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. - Soyed Tuhin Ahmed; Kamal Danouchi; Christopher Münch; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (NANOARCH, 2022)

MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge. - Theo Soriano; David Novo; Guillaume Prenat; Gregory di Pendina; Pascal Benoit (VLSI-SoC, 2022)

A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. - Etienne Becle; Guillaume Prenat; Philippe Talatchian; Lorena Anghel; Ioan Lucian Prejbeanu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (DATE, 2023)

Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. - Kamal Danouchi; Guillaume Prenat; Philippe Talatchian; Louis Hutin; Lorena Anghel (ISVLSI, 2023)

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. - Joao Henrique Quintino Palhares; Yann Beilliard; Jury Sandrini; Franck Arnaud; Kevin Garello; Guillaume Prenat; Lorena Anghel; Fabien Alibart; Dominique Drouin; Philippe Galy (CoRR, 2023)

Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (CoRR, 2023)

Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (CoRR, 2023)

SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. - Soyed Tuhin Ahmed; Kamal Danouchi; Christopher Münch; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. - Ghislain Takam Tchendjou; Kamal Danouchi; Guillaume Prenat; Lorena Anghel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (ACM Trans. Embed. Comput. Syst., 2023)

Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. - Soyed Tuhin Ahmed; Kamal Danouchi; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (DATE, 2024)

NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. - Soyed Tuhin Ahmed; Kamal Danouchi; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (DATE, 2024)

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. - Soyed Tuhin Ahmed; Kamal Danouchi; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (ETS, 2024)

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. - Soyed Tuhin Ahmed; Michael Hefenbrock; Guillaume Prenat; Lorena Anghel; Mehdi B. Tahoori (CoRR, 2024)

Temperature and Drift-Aware High-Level PCM-based Array Model for Reliable Hardware IMC Design. - V. Viollet; E. Esmanhotto; M. Allegra; Matteo Baldo; Guillaume Prenat; Lorena Anghel; X. Lecoq (IRPS, 2025)