On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. - Guillaume Renaud; Manuel J. Barragán; Salvador Mir; Marc Sabut (ATS, 2014)

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda; Guillaume Renaud; Manuel J. Barragán; Salvador Mir (ETS, 2016)

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. - Guillaume Renaud; Manuel J. Barragán; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Hervé Naudet (J. Electron. Test., 2016)

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. - Guillaume Renaud; Marc Margalef-Rovira; Manuel J. Barragán; Salvador Mir (VTS, 2017)

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. - Guillaume Renaud; Mamadou Diallo; Manuel J. Barragán; Salvador Mir (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An overview of Hybridization of Power sources for Ancillary Service. - Ritu Raj Shrivastwa; Ahmad Hably; Seddik Bacha; Hugo Mesnage; Guillaume Renaud (ICIT, 2020)