Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. - Guillaume Savaton; Emmanuel Casseau; Eric Martin 001 (Signal Process., 2006)

Simulator generation using an automaton based pipeline model for timing analysis. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet; Guillaume Savaton (IMCSIT, 2008)

Instruction set simulator generation using HARMLESS, a new hardware architecture description language. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet; Guillaume Savaton (SimuTools, 2009)

An Architecture Description Language for Embedded Hardware Platforms. - Guillaume Savaton; Jean-Luc Béchennec; Mikaël Briday; Rola Kassem (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2011)

Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Guillaume Savaton; Yvon Trinquet (J. Syst. Archit., 2012)

Towards Functional Model Transformations with OCL. - Frédéric Jouault; Olivier Beaudoux; Matthias Brun 001; Mickael Clavreul; Guillaume Savaton (ICMT, 2015)