An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

SafeSU: an Extended Statistics Unit for Multicore Timing Interference. - Guillem Cabo; Francisco Bas; Ruben Lorenzo; David Trilla; Sergi Alcaide; Miquel Moretó; Carles Hernández 001; Jaume Abella 001 (ETS, 2021)

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping. - Francisco Bas; Sergi Alcaide; Ruben Lorenzo; Guillem Cabo; Guillermo Gil; Oriol Sala; Fabio Mazzocchetti; David Trilla; Jaume Abella 001 (IOLTS, 2021)

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation. - Oriol Sala; Sergi Alcaide; Guillem Cabo; Francisco Bas; Ruben Lorenzo; Pedro Benedicte; David Trilla; Guillermo Gil; Fabio Mazzocchetti; Jaume Abella 001 (IOLTS, 2021)

SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores. - Francisco Bas; Pedro Benedicte; Sergi Alcaide; Guillem Cabo; Fabio Mazzocchetti; Jaume Abella 001 (DATE, 2022)

SafeSU-2: a Safe Statistics Unit for Space MPSoCs. - Guillem Cabo; Sergi Alcaide; Carles Hernández 001; Pedro Benedicte; Francisco Bas; Fabio Mazzocchetti; Jaume Abella 001 (DATE, 2022)

De-RISC: A Complete RISC-V Based Space-Grade Platform. - Nils-Johan Wessman; Fabio Malatesta; Stefano Ribes; Jan Andersson; Antonio García-Vilanova; Miguel Masmano; Vicente Nicolau; Paco Gomez; Jimmy Le Rhun; Sergi Alcaide; Guillem Cabo; Francisco Bas; et al. (DATE, 2022)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

SafeX: Open Source Hardware and Software Components for Safety-Critical Systems. - Sergi Alcaide; Guillem Cabo; Francisco Bas; Pedro Benedicte; Francisco Fuentes; Feng Chang; Ilham Lasfar; Ramon Canal; Jaume Abella 001 (FDL, 2022)

SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications. - Ramon Canal; Francisco Bas; Sergi Alcaide; Guillem Cabo; Pedro Benedicte; Francisco Fuentes; Feng Chang; Ilham Lasfar; Jaume Abella 001 (SAMOS, 2022)

SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks. - Fabio Mazzocchetti; Sergi Alcaide; Francisco Bas; Pedro Benedicte; Guillem Cabo; Feng Chang; Francisco Fuentes; Jaume Abella 001 (CoRR, 2022)

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform. - Pablo Andreu; Carles Hernández 001; Tomás Picornell; Pedro López 001; Sergi Alcaide; Francisco Bas; Pedro Benedicte; Guillem Cabo; Feng Chang; Francisco Fuentes; Jaume Abella 001 (CoRR, 2022)

SafeSU-2L: An Advanced Multicore Interference Statistics Unit for a RISC-V Space SoC. - Francisco Bas; Sergi Alcaide; Guillem Cabo; Ilham Lasfar; Feng Chang; Francisco Fuentes; Ramon Canal; Pedro Benedicte; Juan Carlos Rodriguez; Jaume Abella 001 (IEEE Trans. Aerosp. Electron. Syst., 2025)