Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. - Guillermo Payá Vayá; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Francisco José Mora Mas (FPL, 2003)

A new inverse discrete wavelet packet transform architecture. - Guillermo Payá Vayá; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Vicente Herrero-Bosch; Joaquín Cerdá (ISSPA (2), 2003)

Implementing a Margolus Neighborhood Cellular Automata on a FPGA. - Joaquín Cerdá; Rafael Gadea Gironés; Guillermo Payá Vayá (IWANN (2), 2003)

FPGA Custom DSP for ECG Signal Analysis and Compression. - Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá; Ricardo José Colom-Palero; Rafael Gadea Gironés; J. Belenguer (FPL, 2004)

Architectures for ICT on FPGA. - Arturo Méndez Patiño; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá (FPT, 2004)

2D-DCT on FPGA by polynomial transformation in two-dimensions. - Arturo Méndez Patiño; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá (ISCAS (3), 2004)

RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. - Guillermo Payá Vayá; Javier Martín-Langerwerf; Peter Pirsch (SAMOS, 2005)

Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Piriya Taptimthong; Peter Pirsch (ARCS, 2007)

RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Peter Pirsch (DSD, 2007)

Design Space Exploration of Media Processors: A Parameterized Scheduler. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Piriya Taptimthong; Peter Pirsch (ICSAMOS, 2007)

ChipDesign: from theory to real world. - Guillermo Payá-Vayá; Thomas Jambor; Konstantin Septinus; Sebastian Hesselbarth; Holger Flatt; Marc Freisfeld; Peter Pirsch (WCAE, 2007)

An Enhanced DMA Controller in SIMD Processors for Video Applications. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Sören Moch; Peter Pirsch (ARCS, 2009)

Instruction merging to increase parallelism in VLIW architectures. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Florian Giesemann; Holger Blume; Peter Pirsch (SoC, 2009)

A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Holger Blume; Peter Pirsch (ASAP, 2010)

A Multi-Shared Register File Structure for VLIW Processors. - Guillermo Payá-Vayá; Javier Martín-Langerwerf; Peter Pirsch (J. Signal Process. Syst., 2010)

Design and analysis of a generic VLIW processor for multimedia applications. - Guillermo Payá Vayá (2011)

ASEV - Automatic situation assessment for event-driven video analysis. - Michele Fenzi; Jörn Ostermann; Nico Mentzer; Guillermo Payá-Vayá; Holger Blume; Tu Ngoc Nguyen; Thomas Risse 001 (AVSS, 2014)

Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms. - Oliver Jakob Arndt; Daniel Becker 001; Florian Giesemann; Guillermo Payá-Vayá; Christopher Bartels; Holger Blume (ICSAMOS, 2014)

A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications. - Florian Giesemann; Guillermo Payá-Vayá; Holger Blume; Matthias Limmer; Werner Ritter (ICSAMOS, 2014)

Instruction-set extension for an ASIP-based SIFT feature extraction. - Nico Mentzer; Guillermo Payá-Vayá; Holger Blume; Nora von Egloffstein; Werner Ritter (ICSAMOS, 2014)

Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices. - Julian Hartig; Lukas Gerlach 001; Guillermo Payá-Vayá; Holger Blume (SiPS, 2014)

Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture. - Stephan Nolting; Guillermo Payá-Vayá; Florian Giesemann; Holger Blume (ARC, 2015)

A Synthesizable Temperature Sensor on FPGA Using DSP-Slices for Reduced Calibration Overhead and Improved Stability. - Christopher Bartels; Chao Zhang; Guillermo Payá-Vayá; Holger Blume (ARCS, 2015)

FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design. - Rochus Nowosielski; Lukas Gerlach 001; Stephan Bieband; Guillermo Payá-Vayá; Holger Blume (DATE, 2015)

A mobile SoC-based platform for evaluating hearing aid algorithms and architectures. - Christopher Seifert; Guillermo Payá-Vayá; Holger Blume; Tobias Herzke; Volker Hohmann (ICCE-Berlin, 2015)

FNOCEE: A framework for NoC evaluation by FPGA-based emulation. - Daniel Pfefferkorn; Achim Schmider; Guillermo Payá-Vayá; Martin Neuenhahn; Holger Blume (SAMOS, 2015)

An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors. - Lukas Gerlach 001; Guillermo Payá-Vayá; Holger Blume (SiPS, 2015)

Customized high performance low power processor for binaural speaker localization. - Nicolai Behmann; Christopher Seifert; Guillermo Payá-Vayá; Holger Blume; Pekka Jääskeläinen; Joonas Multanen; Heikki Kultala; Jarmo Takala; Joachim Thiemann; Steven van de Par (ICECS, 2016)

Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture. - Stephan Nolting; Guillermo Payá-Vayá; Florian Giesemann; Holger Blume; Sebastian Niemann; Christian Müller-Schloer (IPDPS Workshops, 2016)

Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. - Lukas Gerlach 001; Guillermo Payá-Vayá; Holger Blume (SiPS, 2016)

Performance monitoring for automatic speech recognition in noisy multi-channel environments. - Bernd T. Meyer; Sri Harish Reddy Mallidi; Angel Mario Castro Martinez; Guillermo Payá-Vayá; Hendrik Kayser; Hynek Hermansky (SLT, 2016)

Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction. - Nico Mentzer; Guillermo Payá-Vayá; Holger Blume (J. Signal Process. Syst., 2016)

Application-specific soft-core vector processor for advanced driver assistance systems. - Stephan Nolting; Florian Giesemann; Julian Hartig; Achim Schmider; Guillermo Payá-Vayá (FPL, 2017)

Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices. - Stephan Nolting; Lin Liu; Guillermo Payá-Vayá (FPL, 2017)

Tool-supported design space exploration of a processor system for SIFT-feature detection. - Julian Hartig; Guillermo Payá-Vayá; Henrik Heymann; Holger Blume (ICCE-Berlin, 2017)

Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor. - Christopher Seifert; Joachim Thiemann; Lukas Gerlach 001; Tobias Volkmar; Guillermo Payá-Vayá; Holger Blume; Steven van de Par (ICME, 2017)

A fair comparison of adders in stochastic regime. - Ardalan Najafi; Moritz Weißbrich; Guillermo Payá Vayá; Alberto García Ortiz (PATMOS, 2017)

Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP. - Lukas Gerlach 001; Guillermo Payá-Vayá; Shuang Liu 009; Moritz Weißbrich; Holger Blume; Daniel Marquardt; Simon Doclo (SAMOS, 2017)

Using a genetic algorithm approach to reduce register file pressure during instruction scheduling. - Florian Giesemann; Guillermo Payá-Vayá; Lukas Gerlach 001; Holger Blume; Fabian Pflug; Gabriele von Voigt (SAMOS, 2017)

Balanced application-specific processor system for efficient SIFT-feature detection. - Julian Hartig; Guillermo Payá-Vayá; Nico Mentzer; Holger Blume (SAMOS, 2017)

Guest Editorial: Special Issue on the 2015 International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV). - Guillermo Payá-Vayá; Andreas Gerstlauer (Int. J. Parallel Program., 2017)

Small footprint synthesizable temperature sensor for FPGA devices. - Guillermo Payá-Vayá; Christopher Bartels; Holger Blume (J. Syst. Archit., 2017)

Cross-layer fault-space pruning for hardware-assisted fault injection. - Christian Dietrich 001; Achim Schmider; Oskar Pusz; Guillermo Payá Vayá; Daniel Lohmann (DAC, 2018)

Transport-Triggered Soft Cores. - Pekka Jääskeläinen; Aleksi Tervo; Guillermo Payá Vayá; Timo Viitanen; Nicolai Behmann; Jarmo Takala; Holger Blume (IPDPS Workshops, 2018)

Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics. - Ardalan Najafi; Moritz Weißbrich; Guillermo Payá-Vayá; Alberto García Ortiz (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A Coding Approach to Improve the Energy Efficiency of Approximate NoCs. - Amir Najafi 001; Lennart Bamberg; Guillermo Payá Vayá; Alberto García Ortiz (ReCoSoC, 2019)

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments. - Sven Gesper; Moritz Weißbrich; Stephan Nolting; Tobias Stuckenberg; Pekka Jääskeläinen; Holger Blume; Guillermo Payá-Vayá (SAMOS, 2019)

KAVUAKA: A Low Power Application Specific Hearing Aid Processor. - Lukas Gerlach 001; Guillermo Payá-Vayá; Holger Blume (VLSI-SoC, 2019)

FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. - Moritz Weißbrich; Lukas Gerlach 001; Holger Blume; Ardalan Najafi; Alberto García Ortiz; Guillermo Payá-Vayá (Integr., 2019)

Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture. - Stephan Nolting; Guillermo Payá-Vayá; Florian Giesemann; Holger Blume; Sebastian Niemann; Christian Müller-Schloer (J. Parallel Distributed Comput., 2019)

Online stereo camera calibration for automotive vision based on HW-accelerated A-KAZE-feature extraction. - Nico Mentzer; Jannik Mahr; Guillermo Payá-Vayá; Holger Blume (J. Syst. Archit., 2019)

Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction. - Moritz Weißbrich; Alberto García Ortiz; Guillermo Payá-Vayá (J. Syst. Archit., 2019)

DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters. - Angel Mario Castro Martinez; Lukas Gerlach 001; Guillermo Payá-Vayá; Hynek Hermansky; Jasper Ooster; Bernd T. Meyer (Speech Commun., 2019)

CereBridge: An Efficient, FPGA-based Real-Time Processing Platform for True Mobile Brain-Computer Interfaces. - Marc-Nils Wahalla; Guillermo Payá Vayá; Holger Blume (EMBC, 2020)

Issue-Slot Based Predication Encoding Technique for VLIW Processors. - Lukas Gerlach 001; Fabian Stuckmann; Holger Blume; Guillermo Payá-Vayá (MOCAST, 2020)

Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing Aids. - Jens Karrenbauer; Lukas Gerlach 001; Guillermo Payá-Vayá; Holger Blume (MOCAST, 2020)

A Runtime-Reconfigurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures. - Moritz Weißbrich; Alberto García Ortiz; Guillermo Payá-Vayá (MOCAST, 2020)

Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. - Florian Giesemann; Lukas Gerlach 001; Guillermo Payá-Vayá (J. Signal Process. Syst., 2020)

PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores. - Fabian Stuckmann; Pasha A. Fistanto; Guillermo Payá-Vayá (MOCAST, 2021)

Using Genetic Algorithms to Optimize the Instruction-Set Encoding on Processor Cores. - Moritz Weißbrich; Javier Andrés Moreno-Medina; Guillermo Payá-Vayá (MOCAST, 2021)

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. - Sven Gesper; Moritz Weißbrich; Tobias Stuckenberg; Pekka Jääskeläinen; Holger Blume; Guillermo Payá-Vayá (Int. J. Parallel Program., 2021)

A Silicon-Proof Controller System for Flexible Ultra-Low-Power Energy Harvesting Platforms. - Moritz Weißbrich; Holger Blume; Guillermo Payá-Vayá (MOCAST, 2022)

NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers. - Moritz Weißbrich; Guillermo Payá-Vayá (SAMOS, 2022)

A Survey on Application Specific Processor Architectures for Digital Hearing Aids. - Lukas Gerlach 001; Guillermo Payá-Vayá; Holger Blume (J. Signal Process. Syst., 2022)

TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. - Johannes Knödtel; Hector Gerardo Muñoz Hernandez; Alexander Lehnert; Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Marc Reichenbach (ARC, 2023)

Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology. - Eike Trumann; Gia Bao Thieu; Johannes Schmechel; Kirsten Weide-Zaage; Katharina Schmidt; Dorian Hagenah; Guillermo Payá Vayá (ARC, 2023)

Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency. - Michael Beyer; Sven Gesper; Andre Guntoro; Guillermo Payá-Vayá; Holger Blume (ASAP, 2023)

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Christoph Riggers; Oliver Renke; Till Fiedler; Jakob Marten; Tobias Stuckenberg; Holger Blume; Christian Weis; Lukas Steiner; Chirag Sudarshan; et al. (DATE, 2023)

N2V2PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture. - Sven Gesper; Gia Bao Thieu; Daniel Köhler; Markus Kock; Tim Berthold; Oliver Renke; Holger Blume; Guillermo Payá-Vayá (ICCE-Berlin, 2023)

PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations. - Sven Gesper; Fabian Stuckmann; Lucy Wöbbekind; Guillermo Payá-Vayá (SAMOS, 2023)

A 4μW Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle. - Luciano S. Martínez Rau; Moritz Weißbrich; Guillermo Payá-Vayá (J. Signal Process. Syst., 2023)

Multi-Level Prototyping of a Vertical Vector AI Processing System. - Frederik Kautz; Sven Gesper; Gia Bao Thieu; Hans-Martin Blüthgen; Holger Blume; Guillermo Payá-Vayá (ASAP, 2024)

A Graph Neural Network Approach to Improve List Scheduling Heuristics Under Register-Pressure. - Fabian Stuckmann; Guillermo Payá-Vayá (MOCAST, 2024)

A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs. - Moritz Weißbrich; Alexander Meyer; Adilet Dossanov; Vadim Issakov; Guillermo Payá-Vayá (NorCAS, 2024)

A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor. - Sven Gesper; Daniel Köhler; Gia Bao Thieu; Jasper Homann; Frank Meinl; Holger Blume; Guillermo Payá-Vayá (SAMOS, 2024)

NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems. - Moritz Weißbrich; Germain Seidlitz; Guillermo Payá-Vayá (SAMOS, 2024)

Energy-Aware Register Allocation for VLIW Processors. - Fabian Stuckmann; Moritz Weißbrich; Guillermo Payá-Vayá (J. Signal Process. Syst., 2024)

DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá (ACM Trans. Archit. Code Optim., 2025)