A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS. - Jaehong Jung; Kyungmin Lee; Gunwoo Kong; Baekmin Lim; Seungjin Kim; Seunghyun Oh; Jongwoo Lee (VLSI Technology and Circuits, 2023)