Highly Efficient Load-Balanced Dataflow for SpGEMMs on Systolic Arrays. - Guocheng Zhao; Yongxiang Cao (ACM Great Lakes Symposium on VLSI, 2024)

Compression Format and Systolic Array Structure Co-design for Accelerating Sparse Matrix Multiplication in DNNs. - Yongxiang Cao; Jixiang Jiang; Guocheng Zhao; Wei Wang; Hongxu Jiang; Yanfei Song (ICA3PP (4), 2024)