Thermal-Aware 3D IC Placement Via Transformation. - Jason Cong; Guojie Luo; Jie Wei; Yan Zhang (ASP-DAC, 2007)

Highly efficient gradient computation for density-constrained analytical placement methods. - Jason Cong; Guojie Luo (ISPD, 2008)

Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. - Jason Cong; Guojie Luo; Eric Radke (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A multilevel analytical placement for 3D ICs. - Jason Cong; Guojie Luo (ASP-DAC, 2009)

Logic-on-logic 3D integration and placement. - Thorlindur Thorolfsson; Guojie Luo; Jason Cong; Paul D. Franzon (3DIC, 2010)

An analytical placer for mixed-size 3D placement. - Jason Cong; Guojie Luo (ISPD, 2010)

Advances and Challenges in 3D Physical Design. - Jason Cong; Guojie Luo (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Thermal-aware cell and through-silicon-via co-placement for 3D ICs. - Jason Cong; Guojie Luo; Yiyu Shi 001 (DAC, 2011)

Early chip planning cockpit. - Jeonghee Shin; John A. Darringer; Guojie Luo; Alan J. Weger; Charles L. Johnson (DATE, 2011)

A unified optimization framework for simultaneous gate sizing and placement under density constraints. - Jason Cong; John Lee 002; Guojie Luo (ISCAS, 2011)

Physical hierarchy exploration of 3D processors. - Guojie Luo (ISOCC, 2011)

Floorplanning challenges in early chip planning. - Jeonghee Shin; John A. Darringer; Guojie Luo; Merav Aharoni; Alexey Lvov; Gi-Joon Nam; Michael B. Healy (SoCC, 2011)

Memory partitioning and scheduling co-optimization in behavioral synthesis. - Peng Li 031; Yuxin Wang; Peng Zhang 007; Guojie Luo; Tao Wang 004; Jason Cong (ICCAD, 2012)

Towards layout-friendly high-level synthesis. - Jason Cong; Bin Liu 006; Guojie Luo; Raghu Prabhakar (ISPD, 2012)

Optimizing routability in large-scale mixed-size placement. - Jason Cong; Guojie Luo; Kalliopi Tsota; Bingjun Xiao (ASP-DAC, 2013)

FF-bond: multi-bit flip-flop bonding at placement. - Chang-Cheng Tsai; Yiyu Shi 001; Guojie Luo; Iris Hui-Ru Jiang (ISPD, 2013)

An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. - Guojie Luo; Yiyu Shi 001; Jason Cong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. - Peng Li 031; Thomas Page; Guojie Luo; Wentai Zhang 001; Pei Wang; Peng Zhang 007; Peter Maass; Ming Jiang 001; Jason Cong (FCCM, 2014)

Analyzing the impact of heterogeneous blocks on FPGA placement quality. - Chang Xu 005; Wentai Zhang 001; Guojie Luo (FPT, 2014)

Rapid design space exploration of two-level unified caches. - Jingyu Deng; Yun Liang 001; Guojie Luo; Guangyu Sun 003 (ISCAS, 2014)

VeLoc: finding your car in the parking lot. - Mingmin Zhao; Ruipeng Gao; Jiaxu Zhu; Tao Ye; Fan Ye 003; Yizhou Wang 001; Kaigui Bian; Guojie Luo; Ming Zhang 004 (SenSys, 2014)

A Fast and Simple Block-Based Approach for Common Path Pessimism Removal in Static Timing Analysis. - Guojie Luo; Baihong Jin; Wentai Zhang 001 (CAD/Graphics, 2015)

FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only). - Wentai Zhang 001; Li Shen; Thomas Page; Guojie Luo; Peng Li 031; Peter Maaß; Ming Jiang 001; Jason Cong (FPGA, 2015)

Accelerate FPGA Routing with Parallel Recursive Partitioning. - Minghua Shen; Guojie Luo (ICCAD, 2015)

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging. - Chang Xu 005; Peixin Li; Guojie Luo; Yiyu Shi 001; Iris Hui-Ru Jiang (ISPD, 2015)

VeTrack: Real Time Vehicle Tracking in Uninstrumented Indoor Environments. - Mingmin Zhao; Tao Ye; Ruipeng Gao; Fan Ye 003; Yizhou Wang 001; Guojie Luo (SenSys, 2015)

VeMap: Indoor Road Map Construction via Smartphone-Based Vehicle Tracking. - Ruipeng Gao; Guojie Luo; Fan Ye 003 (GLOBECOM, 2016)

A fast and accurate approach for common path pessimism removal in static timing analysis. - Baihong Jin; Guojie Luo; Wentai Zhang 001 (ISCAS, 2016)

Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. - Chen Zhang 001; Di Wu 010; Jiayu Sun; Guangyu Sun 003; Guojie Luo; Jason Cong (ISLPED, 2016)

Scaling Up Physical Design: Challenges and Opportunities. - Guojie Luo; Wentai Zhang 001; Jiaxi Zhang 001; Jason Cong (ISPD, 2016)

Sextant: Towards Ubiquitous Indoor Localization Service by Photo-Taking of the Environment. - Ruipeng Gao; Yang Tian; Fan Ye 003; Guojie Luo; Kaigui Bian; Yizhou Wang 001; Tao Wang 004; Xiaoming Li 001 (IEEE Trans. Mob. Comput., 2016)

Multi-Story Indoor Floor Plan Reconstruction via Mobile Crowdsensing. - Ruipeng Gao; Mingmin Zhao; Tao Ye; Fan Ye 003; Guojie Luo; Yizhou Wang 001; Kaigui Bian; Tao Wang 004; Xiaoming Li 001 (IEEE Trans. Mob. Comput., 2016)

Analytical Clustering Score with Application to Postplacement Register Clustering. - Chang Xu 005; Guojie Luo; Peixin Li; Yiyu Shi 001; Iris Hui-Ru Jiang (ACM Trans. Design Autom. Electr. Syst., 2016)

Megrez: Parallelizing FPGA Routing with Strictly-Ordered Partitioning. - Minghua Shen; Guojie Luo (FCCM, 2017)

FPGA Acceleration for Computational Glass-Free Displays. - Zhuolun He; Guojie Luo (FPGA, 2017)

Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion. - Minghua Shen; Guojie Luo (FPGA, 2017)

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. - Chang Xu 005; Gai Liu; Ritchie Zhao; Stephen Yang; Guojie Luo; Zhiru Zhang (FPGA, 2017)

A coordinated synchronous and asynchronous parallel routing approach for FPGAs. - Minghua Shen; Guojie Luo; Nong Xiao 001 (ICCAD, 2017)

Dependency-Aware Parallel Routing for Large-Scale FPGAs. - Minghua Shen; Nong Xiao 001; Guojie Luo (ICCD, 2017)

Search space reduction for the non-exact projective NPNP Boolean matching problem. - Feng Wang 046; Jiaxi Zhang 001; Lange Wu; Wentai Zhang 001; Guojie Luo (ISCAS, 2017)

Tiguan: Energy-aware collision-free control for large-scale connected vehicles. - Minghua Shen; Guojie Luo (ISLPED, 2017)

Smartphone-Based Real Time Vehicle Tracking in Indoor Parking Structures. - Ruipeng Gao; Mingmin Zhao; Tao Ye; Fan Ye 003; Yizhou Wang 001; Guojie Luo (IEEE Trans. Mob. Comput., 2017)

FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos. - Zhuolun He; Hanxian Huang; Ming Jiang 001; Yuanchao Bai; Guojie Luo (FCCM, 2018)

Exploiting Box Expansion and Grid Partitioning for Parallel FPGA Routing. - Minghua Shen; Guojie Luo; Nong Xiao 001 (FCCM, 2018)

DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). - Gai Liu; Ecenur Ustun; Shaojie Xiang; Chang Xu 005; Guojie Luo; Zhiru Zhang (FPGA, 2018)

Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only). - Minghua Shen; Wentai Zhang 001; Nong Xiao 001; Guojie Luo (FPGA, 2018)

BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only). - Minghua Shen; Jiaxi Zhang 001; Nong Xiao 001; Guojie Luo (FPGA, 2018)

Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only). - Wentai Zhang 001; Jiaxi Zhang 001; Minghua Shen; Nong Xiao 001; Guojie Luo (FPGA, 2018)

Adaptive-precision framework for SGD using deep Q-learning. - Wentai Zhang 001; Hanxian Huang; Jiaxi Zhang 001; Ming Jiang 001; Guojie Luo (ICCAD, 2018)

cuMBIR: An Efficient Framework for Low-dose X-ray CT Image Reconstruction on GPUs. - Xiuhong Li; Yun Liang 001; Wentai Zhang 001; Taide Liu; Haochen Li 001; Guojie Luo; Ming Jiang 001 (ICS, 2018)

Accelerating Mobile Applications at the Network Edge with Software-Programmable FPGAs. - Shuang Jiang; Dong He 002; Chenxi Yang; Chenren Xu; Guojie Luo; Yang Chen 001; Yunlu Liu; Jiangwei Jiang (INFOCOM, 2018)

V-PIM: An Analytical Overhead Model for Processing-in-Memory Architectures. - Peichen Xie; Guangyu Sun 003; Feng Wang 046; Guojie Luo (NVMSA, 2018)

Smartphone-Based Indoor Map Construction - Principles and Applications - Ruipeng Gao; Fan Ye 003; Guojie Luo; Jason Cong (Springer, 2018)

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Peng Huang 004; Jinfeng Kang (ASAP, 2019)

An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures. - Wentai Zhang 001; Jiaxi Zhang 001; Minghua Shen; Guojie Luo; Nong Xiao 001 (DATE, 2019)

FTConv: FPGA Acceleration for Transposed Convolution Layers in Deep Neural Networks. - Zhucheng Tang; Guojie Luo; Ming Jiang 001 (FPGA, 2019)

Winograd-Based Real-Time Super-Resolution System on FPGA. - Bizhao Shi; Zhucheng Tang; Guojie Luo; Ming Jiang 001 (FPT, 2019)

Frequency Improvement of Systolic Array-Based CNNs on FPGAs. - Jiaxi Zhang 001; Wentai Zhang 001; Guojie Luo; Xuechao Wei; Yun Liang 001; Jason Cong (ISCAS, 2019)

An Analytical Method of Automatic Alignment for Electron Tomography. - Shuang Wen 001; Guojie Luo (LABELS/HAL-MICCAI/CuRIOUS@MICCAI, 2019)

Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. - Dajiang Liu; Shouyi Yin; Guojie Luo; Jiaxing Shang; Leibo Liu; Shaojun Wei; Yong Feng 002; Shangbo Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Exploring GPU-Accelerated Routing for FPGAs. - Minghua Shen; Guojie Luo; Nong Xiao 001 (IEEE Trans. Parallel Distributed Syst., 2019)

Hardware-assisted Service Live Migration in Resource-limited Edge Computing Systems. - Zhe Zhou 002; Xintong Li; Xiaoyang Wang 006; Zheng Liang 003; Guangyu Sun 003; Guojie Luo (DAC, 2020)

FPGA-accelerated Automatic Alignment for Three-dimensional Tomography. - Shuang Wen 001; Guojie Luo (FCCM, 2020)

Evaluating Low-Memory GEMMs for Convolutional Neural Network Inference on FPGAs. - Wentai Zhang 001; Ming Jiang 001; Guojie Luo (FCCM, 2020)

FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction. - Linjun Qiao; Guojie Luo; Wentai Zhang 001; Ming Jiang 001 (FPL, 2020)

SaFace: Towards Scenario-aware Face Recognition via Edge Computing System. - Zhe Zhou 002; Bingzhe Wu; Zheng Liang 003; Guangyu Sun 003; Chenren Xu; Guojie Luo (HotEdge, 2020)

Dual-Output LUT Merging during FPGA Technology Mapping. - Feng Wang 046; Liren Zhu; Jiaxi Zhang 001; Lei Li; Yang Zhang; Guojie Luo (ICCAD, 2020)

Serial-Equivalent Static and Dynamic Parallel Routing for FPGAs. - Minghua Shen; Wentai Zhang 001; Guojie Luo; Nong Xiao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

EEPC: A Framework for Energy-Efficient Parallel Control of Connected Cars. - Minghua Shen; Guojie Luo; Nong Xiao 001 (IEEE Trans. Parallel Distributed Syst., 2020)

Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping. - Yijiang Guo; Jiarui Wang; Jiaxi Zhang 001; Guojie Luo (DAC, 2021)

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. - Zhe Zhou 002; Bizhao Shi; Zhe Zhang 006; Yijin Guan; Guangyu Sun 003; Guojie Luo (DAC, 2021)

TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths. - Zhengzheng Ma; Guojie Luo (FCCM, 2021)

FPGA-accelerated Iterative Reconstruction for Transmission Electron Tomography. - Linjun Qiao; Guojie Luo; Wentai Zhang 001; Ming Jiang 001 (FCCM, 2021)

Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning. - Jiaxi Zhang 001; Liwei Ni; Shenggen Zheng; Hao Liu; Xiangfu Zou; Feng Wang 046; Guojie Luo (ICCAD, 2021)

SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes. - Feng Wang 046; Guangyu Sun 003; Guojie Luo (ICCAD, 2021)

An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode. - Jiaxi Zhang 001; Tao Yang 031; Qingzheng Li; Bo Zhou; Yang Yang; Guojie Luo; Jianping Shi (ISCAS, 2021)

Feasibility study of practical vital sign detection using millimeter-wave radios. - Weicheng Wang; Zhenhua Jia; Chenren Xu; Guojie Luo; Daqing Zhang 001; Ning An 001; Yanyong Zhang (CCF Trans. Pervasive Comput. Interact., 2021)

Area Efficient Pattern Representation of Binary Neural Networks on RRAM. - Feng Wang 046; Guojie Luo; Guang-Yu Sun 003; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (J. Comput. Sci. Technol., 2021)

FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction. - Wentai Zhang 001; Linjun Qiao; William Hsu; Yong Cui; Ming Jiang 001; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Combining Static and Dynamic Load Balance in Parallel Routing for FPGAs. - Minghua Shen; Guojie Luo; Nong Xiao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Jinfeng Kang; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Coarse-Grained Parallel Routing With Recursive Partitioning for FPGAs. - Minghua Shen; Guojie Luo; Nong Xiao 001 (IEEE Trans. Parallel Distributed Syst., 2021)

EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). - Jiaxi Zhang 001; Qiuyang Gao; Yijiang Guo; Bizhao Shi; Guojie Luo (ASP-DAC, 2022)

Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks. - Yijiang Guo; Xinming Wei; Jiaxi Zhang 001; Guojie Luo (ICCD, 2022)

ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs. - Gauthaman Murali; Sandra Maria Shaji; Anthony Agnesina; Guojie Luo; Sung Kyu Lim (ISPD, 2022)

The Case for FPGA-Based Edge Computing. - Chenren Xu; Shuang Jiang; Guojie Luo; Guangyu Sun 003; Ning An 001; Gang Huang 001; Xuanzhe Liu (IEEE Trans. Mob. Comput., 2022)

OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. - Jing Mai; Jiarui Wang; Zhixiong Di; Guojie Luo; Yun Liang 001; Yibo Lin (ASICON, 2023)

GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs. - Xinming Wei; Jiaxi Zhang 001; Guojie Luo (DAC, 2023)

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. - Jiaxi Zhang 001; Shenggen Zheng; Liwei Ni; Huawei Li 001; Guojie Luo (DATE, 2023)

Weave: Abstraction for Accelerator Integration of Generated Modules. - Tuo Dai; Bizhao Shi; Guojie Luo (FPGA, 2023)

An Efficient Dataflow for Convolutional Generative Models. - Zhengzheng Ma; Guojie Luo (ICFPT, 2023)

F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGA. - Bizhao Shi; Jieran Zhang; Guojie Luo (ICFPT, 2023)

Fast Exact NPN Classification with Influence-Aided Canonical Form. - Yonghe Zhang; Liwei Ni; Jiaxi Zhang 001; Guojie Luo; Huawei Li 001; Shenggen Zheng (ICCAD, 2023)

RF-SIFTER: Sifting Signals at Layer-0.5 to Mitigate Wideband Cross-Technology Interference for IoT. - Xiong Wang 006; Jun Huang 001; Bizhao Shi; Zhe Ou; Guojie Luo; Linghe Kong; Daqing Zhang 001; Chenren Xu (MobiCom, 2023)

Per-RMAP: Feasibility-Seeking and Superiorization Methods for Floorplanning with I/O Assignment. - Shan Yu; Yair Censor; Ming Jiang 001; Guojie Luo (CoRR, 2023)

iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library. - Xingquan Li; Simin Tao; Zengrong Huang; Shijian Chen; Zhisheng Zeng; Liwei Ni; Zhipeng Huang 009; Chunan Zhuang; Hongxi Wu; Weiguo Li; Xueyan Zhao; He Liu; et al. (CoRR, 2023)

MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA. - Liwei Ni; Zonglin Yang; Jiaxi Zhang 001; Changhong Feng; Jianhua Liu; Guojie Luo; Huawei Li 001; Biwei Xie; Xingquan Li (CoRR, 2023)

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. - Bizhao Shi; Jiaxi Zhang 001; Zhuolun He; Xuechao Wei; Sicheng Li 001; Guojie Luo; Hongzhong Zheng; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA. - Zhengzheng Ma; Tuo Dai; Xuechao Wei; Guojie Luo (ACM Trans. Embed. Comput. Syst., 2023)

iEDA: An Open-source infrastructure of EDA. - Xingquan Li; Zengrong Huang; Simin Tao; Zhipeng Huang 009; Chunan Zhuang; Hao Wang; Yifan Li; Yihang Qiu; Guojie Luo; Huawei Li 001; Haihua Shen; Mingyu Chen 001; et al. (ASPDAC, 2024)

G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning. - Tuo Dai; Bizhao Shi; Guojie Luo (DAC, 2024)

PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. - Bizhao Shi; Tuo Dai; Jiaxi Zhang 001; Xuechao Wei; Guojie Luo (DAC, 2024)

PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation. - Sunan Zou; Guojie Luo (DAC, 2024)

WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP. - Tuo Dai; Bizhao Shi; Guojie Luo (DATE, 2024)

SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits. - Zexi Li; Haoran Jin; Kuncai Zhong; Guojie Luo; Runsheng Wang; Weikang Qian (DATE, 2024)

An Endeavor to Industrialize Hardware Fuzzing: Automating NoC Verification in UVM. - Ruiyang Ma; Huatao Zhao; Jiayi Huang 001; Shijian Zhang; Guojie Luo (DATE, 2024)

BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (DATE, 2024)

ImageMap: Enabling Efficient Mapping from Image Processing DSL to CGRA. - Bizhao Shi; Tuo Dai; Sunan Zou; Xinming Wei; Guojie Luo (Euro-Par (1), 2024)

Incremental SAT-based Exact Synthesis. - Sunan Zou; Jiaxi Zhang 001; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2024)

AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration. - Xinming Wei; Ziyun Zhang; Sunan Zou; Kaiwen Sun; Jiahao Zhang; Jiaxi Zhang 001; Ping Fan; Guojie Luo (ICCAD, 2024)

MuSA: Multi-Sketch Accelerator with Hybrid Parallelism and Coalesced Memory Organization. - Sunan Zou; Bizhao Shi; Ziyun Zhang; Guojie Luo (ICCD, 2024)

Rethinking IC Layout Vulnerability: Simulation-Based Hardware Trojan Threat Assessment with High Fidelity. - Xinming Wei; Jiaxi Zhang 001; Guojie Luo (SP, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on the Versal ACAP Architecture. - Tuo Dai; Bizhao Shi; Guojie Luo (CoRR, 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

VerilogReader: LLM-Aided Hardware Test Generation. - Ruiyang Ma; Yuxin Yang; Ziqian Liu; Jiaxi Zhang 001; Min Li 019; Junhua Huang; Guojie Luo (CoRR, 2024)

OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis. - Liwei Ni; Rui Wang; Miao Liu; Xingyu Meng; Xiaoze Lin; Junfeng Liu; Guojie Luo; Zhufei Chu; Weikang Qian; Xiaoyan Yang; Biwei Xie; Xingquan Li; et al. (CoRR, 2024)

PowerSyn: A Logic Synthesis Framework With Early Power Optimization. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Weave: Abstraction and Integration Flow for Accelerators of Generated Modules. - Tuo Dai; Bizhao Shi; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Bridging the Gap between Hardware Fuzzing and Industrial Verification. - Ruiyang Ma; Tianhao Wei; Jiaxi Zhang 001; Chun Yang; Jiangfang Yi; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2025)

TACPlace: Ultrafast Thermal-Aware Chiplet Placement with Feasibility Seeking. - Shan Yu; Haiyang Liu; Xinming Wei; Bizhao Shi; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2025)

NoCFuzzer: Automating NoC Verification in UVM. - Ruiyang Ma; Jiayi Huang 001; Shijian Zhang; Yuan Xie 001; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Floorplanning With I/O Assignment via Feasibility-Seeking and Superiorization Methods. - Shan Yu; Yair Censor; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Pseudo-Knowledge Graph: Meta-Path Guided Retrieval and In-Graph Text for RAG-Equipped LLM. - Yuxin Yang; Haoyang Wu; Tao Wang 004; Jia Yang; Hao Ma; Guojie Luo (CoRR, 2025)

UltraSketchLLM: Saliency-Driven Sketching for Ultra-Low Bit LLM Compression. - Sunan Zou; Ziyun Zhang; Xueting Sun; Guojie Luo (CoRR, 2025)

Agent.xpu: Efficient Scheduling of Agentic LLM Workloads on Heterogeneous SoC. - Xinming Wei; Jiahao Zhang; Haoran Li; Jiayu Chen; Rui Qu; Maoliang Li; Xiang Chen; Guojie Luo (CoRR, 2025)

Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation. - Ruiyang Ma; Daikang Kuang; Ziqian Liu; Jiaxi Zhang 001; Ping Fan; Guojie Luo (CoRR, 2025)