A FPGA based intra-parallel architecture for PageRank graph processing. - Guoqiang Mei; Rui Hao; Jiangwei Wang; Hongwei Kan; Rengang Li (EDGE, 2020)

HLS Based Ultra-low Latency FAST Protocol Decoder. - Hongwei Kan; Rui Hao; Jiangwei Wang; Guoqiang Mei; Dongdong Su; Songqing Deng (CSAE, 2021)

A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. - Bonan Yan; Jeng-Long Hsu; Pang-Cheng Yu; Chia-Chi Lee; Yaojun Zhang; Wenshuo Yue; Guoqiang Mei; Yuchao Yang 001; Yue Yang; Hai Li 001; Yiran Chen 001; Ru Huang 001 (ISSCC, 2022)