Low Power Schedule Algorithm for Embedded Multimedia Applications Basing on Imagine-L Processor. - Shan Cao; Zhaolin Li; Zhixiang Chen 003; Guoyue Jiang; Shaojun Wei (HPCC-ICESS, 2012)

A power-efficient network-on-chip for multi-core stream processors. - Guoyue Jiang; Fang Wang; Zhaolin Li; Shaojun Wei (ASICON, 2013)

Compiler-assisted leakage energy optimization of media applications on stream architectures. - Shan Cao; Zhaolin Li; Zhixiang Chen 003; Guoyue Jiang; Shaojun Wei (ISQED, 2013)

Energy-efficient stream task scheduling scheme for embedded multimedia applications on multi-issued stream architectures. - Shan Cao; Zhaolin Li; Fang Wang; Guoyue Jiang; Zhixiang Chen 003; Shaojun Wei (J. Syst. Archit., 2013)

A High-Utilization Scheduling Schemeof Stream Programs on ClusteredVLIW Stream Architectures. - Guoyue Jiang; Zhaolin Li; Fang Wang; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2014)

Scheduling stream programs with improving arithmetic unit usage on NoC-based VLIW multi-core architectures. - Guoyue Jiang; Zhaolin Li; Fang Wang; Shaojun Wei (Conf. Computing Frontiers, 2015)

Mapping of Embedded Applications on Hybrid Networks-on-Chip with Multiple Switching Mechanisms. - Guoyue Jiang; Zhaolin Li; Fang Wang; Shaojun Wei (IEEE Embed. Syst. Lett., 2015)

A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks. - Guoyue Jiang; Zhaolin Li; Fang Wang; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

TPU-MLIR: A Compiler For TPU Using MLIR. - Pengchao Hu; Man Lu; Lei Wang; Guoyue Jiang (CoRR, 2022)

Effective Random Test Generation for Deep Learning Compilers. - Luyao Ren; Ziheng Wang; Yingfei Xiong 001; Li Zhang; Guoyue Jiang; Tao Xie 001 (CoRR, 2023)