An Efficient LISP-Execution Architecture with a New Representation for List Structures. - Gurindar S. Sohi; Edward S. Davidson; Janak H. Patel (ISCA, 1985)

Blast: A Machine Architecture for High-Speed List Processing Using Associative Tables (Traversal, Pointers) - Gurindar S. Sohi (1985)

Features of the Structured Memory Access (SMA) Architecture. - Andrew R. Pleszkun; Gurindar S. Sohi; Bassam Z. Kahhaleh; Edward S. Davidson (COMPCON, 1986)

Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. - Kifung C. Cheung; Gurindar S. Sohi; Kewal K. Saluja; Dhiraj K. Pradhan (ISCA, 1987)

The Performance Potential of Multiple Functional Unit Processors. - Andrew R. Pleszkun; Gurindar S. Sohi (ISCA, 1988)

Multiple instruction issue and single-chip processors. - Andrew R. Pleszkun; Gurindar S. Sohi (MICRO, 1988)

Tradeoffs in Instruction Format Design for Horizontal Architectures. - Gurindar S. Sohi; Sriram Vajapeyam (ASPLOS, 1989)

A study of time-redundant fault tolerance techniques for high-performance pipelined computers. - Gurindar S. Sohi; Manoj Franklin; Kewal K. Saluja (FTCS, 1989)

Restricted Fetch&Phi operations for parallel processing. - Gurindar S. Sohi; James E. Smith 001; James R. Goodman (ICS, 1989)

Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. - Steven L. Scott; Gurindar S. Sohi (ISCA, 1989)

On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns. - V. S. Madan; C.-J. Peng; Gurindar S. Sohi (NACLP, 1989)

Performance Analysis of Hierarchical Cache-Consistent Multiprocessors. - Mary K. Vernon; Rajeev Jog; Gurindar S. Sohi (Perform. Evaluation, 1989)

Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. - Gurindar S. Sohi (IEEE Trans. Computers, 1989)

Exploitation of operation-level parallelism in a processor of the CRAY X-MP. - Sriram Vajapeyam; Gurindar S. Sohi; Wei-Chung Hsu (ICCD, 1990)

Scalable Shared-Memory Multiprocessor Architectures. - Shreekant S. Thakkar; Michel Dubois 001; Anthony T. Laundrie; Gurindar S. Sohi; David V. James; Stein Gjessing; Manu Thapar; Bruce Delagi; Michael J. Carlton; Alvin M. Despain (Computer, 1990)

Design and Analysis of a Gracefully Degrading Interleaved Memory System. - Kifung C. Cheung; Gurindar S. Sohi; Kewal K. Saluja; Dhiraj K. Pradhan (IEEE Trans. Computers, 1990)

Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. - Gurindar S. Sohi (IEEE Trans. Computers, 1990)

The use of intermediate memories for low-latency memory access in supercomputer scalar units. - Gurindar S. Sohi; Wei-Chung Hsu (J. Supercomput., 1990)

The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control. - Steven L. Scott; Gurindar S. Sohi (IEEE Trans. Parallel Distributed Syst., 1990)

High-Bandwidth Data Memory Systems for Superscalar Processors. - Gurindar S. Sohi; Manoj Franklin (ASPLOS, 1991)

An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. - Sriram Vajapeyam; Gurindar S. Sohi; Wei-Chung Hsu (ISCA, 1991)

Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors. - MenChow Chiang; Gurindar S. Sohi (SIGMETRICS, 1991)

Dynamic Dependency Analysis of Ordinary Programs. - Todd M. Austin; Gurindar S. Sohi (ISCA, 1992)

The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. - Manoj Franklin; Gurindar S. Sohi (ISCA, 1992)

Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. - Manoj Franklin; Gurindar S. Sohi (MICRO, 1992)

Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. - MenChow Chiang; Gurindar S. Sohi (IEEE Trans. Computers, 1992)

Control flow prediction for dynamic ILP processors. - Dionisios N. Pnevmatikatos; Manoj Franklin; Gurindar S. Sohi (MICRO, 1993)

High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. - Gurindar S. Sohi (IEEE Trans. Computers, 1993)

Guarded Executing and Branch Prediction in Dynamic ILP Processors. - Dionisios N. Pnevmatikatos; Gurindar S. Sohi (ISCA, 1994)

The anatomy of the register file in a multiscalar processor. - Scott E. Breach; T. N. Vijaykumar; Gurindar S. Sohi (MICRO, 1994)

Efficient Detection of All Pointer and Array Access Errors. - Todd M. Austin; Scott E. Breach; Gurindar S. Sohi (PLDI, 1994)

Request Combining in Multiprocessors with Arbitrary Interconnection Networks. - Alvin R. Lebeck; Gurindar S. Sohi (IEEE Trans. Parallel Distributed Syst., 1994)

Streamlining Data Cache Access with Fast Address Calculation. - Todd M. Austin; Dionisios N. Pnevmatikatos; Gurindar S. Sohi (ISCA, 1995)

Multiscalar Processors. - Gurindar S. Sohi; Scott E. Breach; T. N. Vijaykumar (ISCA, 1995)

Zero-cycle loads: microarchitecture support for reducing load latency. - Todd M. Austin; Gurindar S. Sohi (MICRO, 1995)

The microarchitecture of superscalar processors. - James E. Smith 001; Gurindar S. Sohi (Proc. IEEE, 1995)

High-Bandwidth Address Translation for Multiple-Issue Processors. - Todd M. Austin; Gurindar S. Sohi (ISCA, 1996)

ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. - Manoj Franklin; Gurindar S. Sohi (IEEE Trans. Computers, 1996)

Memory Systems. - Doug Burger; James R. Goodman; Gurindar S. Sohi (The Computer Science and Engineering Handbook, 1997)

Dynamic Speculation and Synchronization of Data Dependences. - Andreas Moshovos; Scott E. Breach; T. N. Vijaykumar; Gurindar S. Sohi (ISCA, 1997)

Dynamic Instruction Reuse. - Avinash Sodani; Gurindar S. Sohi (ISCA, 1997)

Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. - Andreas Moshovos; Gurindar S. Sohi (MICRO, 1997)

Dependance Based Prefetching for Linked Data Structures. - Amir Roth; Andreas Moshovos; Gurindar S. Sohi (ASPLOS, 1998)

An Empirical Analysis of Instruction Repetition. - Avinash Sodani; Gurindar S. Sohi (ASPLOS, 1998)

Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. - Gurindar S. Sohi (25 Years ISCA: Retrospectives and Reprints, 1998)

Retrospective: Multiscalar Processors. - Gurindar S. Sohi (25 Years ISCA: Retrospectives and Reprints, 1998)

Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. - Gurindar S. Sohi; Sriram Vajapeyam (25 Years ISCA: Retrospectives and Reprints, 1998)

Understanding the Differences Between Value Prediction and Instruction Reuse. - Avinash Sodani; Gurindar S. Sohi (MICRO, 1998)

Task Selection for a Multiscalar Processor. - T. N. Vijaykumar; Gurindar S. Sohi (MICRO, 1998)

Improving virtual function call target prediction via dependence-based pre-computation. - Amir Roth; Andreas Moshovos; Gurindar S. Sohi (International Conference on Supercomputing, 1999)

Effective Jump-Pointer Prefetching for Linked Data Structures. - Amir Roth; Gurindar S. Sohi (ISCA, 1999)

Read-After-Read Memory Dependence Prediction. - Andreas Moshovos; Gurindar S. Sohi (MICRO, 1999)

The Use of Multithreading for Exception Handling. - Craig B. Zilles; Joel S. Emer; Gurindar S. Sohi (MICRO, 1999)

Speculative Memory Cloaking and Bypassing. - Andreas Moshovos; Gurindar S. Sohi (Int. J. Parallel Program., 1999)

Task Selection for the Multiscalar Architecture. - T. N. Vijaykumar; Gurindar S. Sohi (J. Parallel Distributed Comput., 1999)

Amir Roth: Speculative Multithreaded Processors. - Gurindar S. Sohi (HiPC, 2000)

Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. - Andreas Moshovos; Gurindar S. Sohi (HPCA, 2000)

Understanding the backward slices of performance degrading instructions. - Craig B. Zilles; Gurindar S. Sohi (ISCA, 2000)

A static power model for architects. - J. Adam Butts; Gurindar S. Sohi (MICRO, 2000)

Register integration: a simple and efficient implementation of squash reuse. - Amir Roth; Gurindar S. Sohi (MICRO, 2000)

Memory Dependence Prediction in Multimedia Applications. - Andreas Moshovos; Gurindar S. Sohi (J. Instr. Level Parallelism, 2000)

Microprocessors - 10 Years Back, 10 Years Ahead. - Gurindar S. Sohi (Informatics, 2001)

Speculative Data-Driven Multithreading. - Amir Roth; Gurindar S. Sohi (HPCA, 2001)

A Programmable Co-Processor for Profiling. - Craig B. Zilles; Gurindar S. Sohi (HPCA, 2001)

Execution-based prediction using speculative slices. - Craig B. Zilles; Gurindar S. Sohi (ISCA, 2001)

Speculative Multithreaded Processors. - Gurindar S. Sohi; Amir Roth (Computer, 2001)

Squash Reuse via a Simplified Implementation of Register Integration. - Amir Roth; Gurindar S. Sohi (J. Instr. Level Parallelism, 2001)

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling. - Andreas Moshovos; Gurindar S. Sohi (Proc. IEEE, 2001)

Speculative Versioning Cache. - T. N. Vijaykumar; Sridhar Gopal; James E. Smith 001; Gurindar S. Sohi (IEEE Trans. Parallel Distributed Syst., 2001)

Dynamic dead-instruction detection and elimination. - J. Adam Butts; Gurindar S. Sohi (ASPLOS, 2002)

Out-of-Order Instruction Fetch Using Multiple Sequencers. - Paramjit S. Oberoi; Gurindar S. Sohi (ICPP, 2002)

Characterizing and predicting value degree of use. - J. Adam Butts; Gurindar S. Sohi (MICRO, 2002)

A quantitative framework for automated pre-execution thread selection. - Amir Roth; Gurindar S. Sohi (MICRO, 2002)

Master/slave speculative parallelization. - Craig B. Zilles; Gurindar S. Sohi (MICRO, 2002)

Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. - Andreas Moshovos; Gurindar S. Sohi (IEEE Trans. Computers, 2002)

Parallelism in the Front-End. - Paramjit S. Oberoi; Gurindar S. Sohi (ISCA, 2003)

Exploiting Value Locality in Physical Register Files. - Saisanthosh Balakrishnan; Gurindar S. Sohi (MICRO, 2003)

Coherence decoupling: making use of incoherence. - Jaehyuk Huh 001; Jichuan Chang; Doug Burger; Gurindar S. Sohi (ASPLOS, 2004)

Use-Based Register Caching with Decoupled Indexing. - J. Adam Butts; Gurindar S. Sohi (ISCA, 2004)

Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. - Gurindar S. Sohi (MICRO, 2004)

Characterization of Problem Stores. - Allison L. Holloway; Gurindar S. Sohi (IEEE Comput. Archit. Lett., 2004)

Speculative Incoherent Cache Protocols. - Jaehyuk Huh 001; Doug Burger; Jichuan Chang; Gurindar S. Sohi (IEEE Micro, 2004)

Hardware support for spin management in overcommitted virtual machines. - Philip M. Wells; Koushik Chakraborty; Gurindar S. Sohi (PACT, 2006)

Computation spreading: employing hardware migration to specialize CMP cores on-the-fly. - Koushik Chakraborty; Philip M. Wells; Gurindar S. Sohi (ASPLOS, 2006)

Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. - Saisanthosh Balakrishnan; Gurindar S. Sohi (ISCA, 2006)

Cooperative Caching for Chip Multiprocessors. - Jichuan Chang; Gurindar S. Sohi (ISCA, 2006)

Adapting to Intermittent Faults in Future Multicore Systems. - Philip M. Wells; Koushik Chakraborty; Gurindar S. Sohi (PACT, 2007)

Cooperative cache partitioning for chip multiprocessors. - Jichuan Chang; Gurindar S. Sohi (ICS, 2007)

Adapting to intermittent faults in multicore systems. - Philip M. Wells; Koushik Chakraborty; Gurindar S. Sohi (ASPLOS, 2008)

Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. - Philip M. Wells; Gurindar S. Sohi (HPCA, 2008)

Mixed-mode multicore reliability. - Philip M. Wells; Koushik Chakraborty; Gurindar S. Sohi (ASPLOS, 2009)

Serialization sets: a dynamic dependence-based parallel execution model. - Matthew D. Allen; Srinath Sridharan; Gurindar S. Sohi (PPoPP, 2009)

Dynamic heterogeneity and the need for multicore virtualization. - Philip M. Wells; Koushik Chakraborty; Gurindar S. Sohi (ACM SIGOPS Oper. Syst. Rev., 2009)

Speculatively Multithreaded Architectures. - Gurindar S. Sohi; T. N. Vijaykumar (Multicore Processors and Systems, 2009)

Dataflow execution of sequential imperative programs on multicore architectures. - Gagan Gupta 001; Gurindar S. Sohi (MICRO, 2011)

Efficient, precise-restartable program execution on future multicores. - Gagan Gupta 001; Srinath Sridharan; Gurindar S. Sohi (Hot Chips Symposium, 2012)

Supporting Overcommitted Virtual Machines through Hardware Spin Detection. - Koushik Chakraborty; Philip M. Wells; Gurindar S. Sohi (IEEE Trans. Parallel Distributed Syst., 2012)

Holistic run-time parallelism management for time and energy efficiency. - Srinath Sridharan; Gagan Gupta 001; Gurindar S. Sohi (ICS, 2013)

Welcome program chairs. - Samuel Naffziger; Guri Sohi (Hot Chips Symposium, 2014)

Author retrospective for cooperative cache partitioning for chip multiprocessors. - Jichuan Chang; Gurindar S. Sohi (ICS 25th Anniversary, 2014)

Globally precise-restartable execution of parallel programs. - Gagan Gupta 001; Srinath Sridharan; Gurindar S. Sohi (PLDI, 2014)

Adaptive, efficient, parallel execution of parallel programs. - Srinath Sridharan; Gagan Gupta 001; Gurindar S. Sohi (PLDI, 2014)

Hot Chips 26 [Guest editors' introduction]. - Samuel Naffziger; Guri Sohi (IEEE Micro, 2015)

Revisiting virtual L1 caches: A practical design using dynamic synonym remapping. - Hongil Yoon; Gurindar S. Sohi (HPCA, 2016)

ATM: Approximate Task Memoization in the Runtime System. - Iulian Brumar; Marc Casas; Miquel Moretó; Mateo Valero; Gurindar S. Sohi (IPDPS, 2017)

Filtering Translation Bandwidth with Virtual Caching. - Hongil Yoon; Jason Lowe-Power; Gurindar S. Sohi (ASPLOS, 2018)

Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses. - Vanshika Baoni; Adarsh Mittal; Gurindar S. Sohi (MICRO, 2021)

Special Issue on Hot Chips 33. - Alisa Scherer; Guri Sohi (IEEE Micro, 2022)

Instruction Block Movement with Coupled High-Level Program Sequencing. - Shyam Murthy; Gurindar S. Sohi (CoRR, 2024)

A Non-Traditional Approach to Assisting Data Address Translation. - Shyam Murthy; Gurindar S. Sohi (CoRR, 2024)