16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor. - Gürtaç Yemisçioglu; Peter Lee (MWSCAS, 2012)

Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor. - Gürtaç Yemisçioglu; P. Lee (IET Comput. Digit. Tech., 2015)

Low-Power and Area-Efficient Finite Field Multiplier Architecture Based on Irreducible All-One Polynomials. - Shima Mohaghegh; Gürtaç Yemisçioglu; Ali Muhtaroglu (ISCAS, 2020)

Design of Efficient AI Accelerator Building Blocks in Quantum-Dot Cellular Automata (QCA). - Ahmed Mamdouh; Mbonea Mjema; Gürtaç Yemisçioglu; Satoshi Kondo; Ali Muhtaroglu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials. - Shima Mohaghegh; Satoshi Kondo; Gürtaç Yemisçioglu; Ali Muhtaroglu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)