Clock period constrained minimal buffer insertion in clock trees. - Gustavo E. Téllez; Majid Sarrafzadeh (ICCAD, 1994)

Memory Segmentation to Exploit Sleep Mode Operation. - Amir H. Farrahi; Gustavo E. Téllez; Majid Sarrafzadeh (DAC, 1995)

Activity-driven clock design for low power circuits. - Gustavo E. Téllez; Amir H. Farrahi; Majid Sarrafzadeh (ICCAD, 1995)

On Rectilinear Distance-Preserving Trees. - Gustavo E. Téllez; Majid Sarrafzadeh (ISCAS, 1995)

Unification of Budgeting and Placement. - Majid Sarrafzadeh; David A. Knol; Gustavo E. Téllez (DAC, 1997)

A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. - Fook-Luen Heng; Zhan Chen; Gustavo E. Téllez (ISPD, 1997)

A delay budgeting algorithm ensuring maximum flexibility in placement. - Majid Sarrafzadeh; David A. Knol; Gustavo E. Téllez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Minimal buffer insertion in clock trees with skew and slew rate constraints. - Gustavo E. Téllez; Majid Sarrafzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Exploiting Sleep Mode for Memory Partitioning and Other Applications. - Amir H. Farrahi; Gustavo E. Téllez; Majid Sarrafzadeh (VLSI Design, 1998)

EDA in IBM: past, present, and future. - John A. Darringer; Evan E. Davidson; David J. Hathaway; Bernd Koenemann; Mark A. Lavin; Joseph K. Morrell; Khalid Rahmat; Wolfgang Roesner; Erich C. Schanzenbach; Gustavo E. Téllez; Louise Trevillyan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Activity-driven clock design. - Amir H. Farrahi; Chunhong Chen; Ankur Srivastava 001; Gustavo E. Téllez; Majid Sarrafzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

What makes a design difficult to route. - Charles J. Alpert; Zhuo Li 001; Michael D. Moffitt; Gi-Joon Nam; Jarrod A. Roy; Gustavo E. Téllez (ISPD, 2010)

Design methodology for the IBM POWER7 microprocessor. - Joshua Friedrich; Ruchir Puri; Uwe Brandt; Markus Bühler; Jack DiLullo; Jeremy Hopkins; Mozammel Hossain; Michael A. Kazda; Joachim Keinert; Zahi M. Kurzum; Douglass Lamb; Alice Lee; et al. (IBM J. Res. Dev., 2011)

GLARE: global and local wiring aware routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (DAC, 2012)

Techniques for scalable and effective routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2014)

Detailed Routing Algorithms for Advanced Technology Nodes. - Markus Ahrens; Michael Gester; Niko Klewinghaus; Dirk Müller 003; Sven Peyer; Christian Schulte 002; Gustavo E. Téllez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Interconnect Optimization Considering Multiple Critical Paths. - Jiang Hu 001; Ying Zhou; Yaoguang Wei; Stephen T. Quay; Lakshmi N. Reddy; Gustavo E. Téllez; Gi-Joon Nam (ISPD, 2018)

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques. - Alexey Lvov; Gustavo E. Téllez; Gi-Joon Nam (ISPD, 2018)

Latch Clustering for Timing-Power Co-Optimization. - Chau-Chin Huang; Gustavo E. Téllez; Gi-Joon Nam; Yao-Wen Chang (DAC, 2020)

Self-Aligned Double-Patterning Aware Legalization. - Hua Xiang 001; Gi-Joon Nam; Gustavo E. Téllez; Shyam Ramji; Xiaoqing Xu (DATE, 2020)

LEO: Line End Optimizer for Sub-7nm Technology Nodes. - Diwesh Pandey; Gustavo E. Téllez; James Leland (ISPD, 2022)