A 64×64 CNN universal chip with analog and digital I/O. - Servando Espejo; Rafael Domínguez-Castro; Gustavo Liñán; Ángel Rodríguez-Vázquez (ICECS, 1998)

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips. - Ricardo Carmona; Ignacio Garcia-Vargas; Gustavo Liñán; Rafael Domínguez-Castro; Servando Espejo; Ángel Rodríguez-Vázquez (Int. J. Circuit Theory Appl., 1999)

A Programmable Imager for Very High Speed Cellular Signal Processing. - Elisenda Roca; Servando Espejo-Meana; Rafael Domínguez-Castro; Gustavo Liñán; Ángel Rodríguez-Vázquez (J. VLSI Signal Process., 1999)

Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip. - Gustavo Liñán; Péter Földesy; A. Rodrignez-Vazquez; Servando Espejo; Rafael Domínguez-Castro (ISCAS, 2000)

CMOS design of focal plane programmable array processors. - Ángel Rodríguez-Vázquez; Servando Espejo-Meana; Rafael Domínguez-Castro; Ricardo Carmona-Galán; Gustavo Liñán (ESANN, 2001)

A processing element architecture for high-density focal plane analog programmable array processors. - Gustavo Liñán Cembrano; Servando Espejo-Meana; Rafael Domínguez-Castro; Ángel Rodríguez-Vázquez (ISCAS (3), 2002)

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips. - Ángel Rodríguez-Vázquez; Gustavo Liñán; Servando Espejo-Meana; Rafael Domínguez-Castro (ISCAS (5), 2002)

ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy. - Gustavo Liñán; Servando Espejo; Rafael Domínguez-Castro; Ángel Rodríguez-Vázquez (Int. J. Circuit Theory Appl., 2002)

A 1000FPS@128×128 vision processor with 8-bit digitized I/O. - Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez; Rafael Castro-López; Servando Espejo-Meana (ESSCIRC, 2003)

Analog weight buffering strategy for CNN chips. - Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez; Ricardo Carmona-Galán; Servando Espejo-Meana; Rafael Domínguez-Castro (ISCAS (3), 2003)

ACE16k: A 128x128 Focal Plane Analog Processor with Digital I/O. - Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez; Servando Espejo-Meana; Rafael Domínguez-Castro (Int. J. Neural Syst., 2003)

A modem in CMOS technology for data communication on the low-voltage power line. - Oscar Guerra; Carlos M. Domínguez-Matas; Sara Escalera; José M. García-González; Gustavo Liñán; Rocío del Río; Manuel Delgado-Restituto; Ángel Rodríguez-Vázquez (Integr., 2003)

An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision. - Gustavo Liñán; Servando Espejo-Meana; Rafael Domínguez-Castro; Ángel Rodríguez-Vázquez (J. Circuits Syst. Comput., 2003)

A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O. - Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez; Ricardo Carmona-Galán; Francisco Jiménez-Garrido; Servando Espejo; Rafael Domínguez-Castro (IEEE J. Solid State Circuits, 2004)

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs. - Ángel Rodríguez-Vázquez; Gustavo Liñán Cembrano; L. Carranza; Elisenda Roca Moreno; Ricardo Carmona-Galán; Francisco Jiménez-Garrido; Rafael Domínguez-Castro; Servando Espejo-Meana (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Locust-inspired vision system on chip architecture for collision detection in automotive applications. - L. Carranza; R. Laviana; Sonia Vargas-Sierra; Jorge Cuadri; Gustavo Liñán; Elisenda Roca; Ángel Rodríguez-Vázquez (ISCAS, 2006)

Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems. - Gustavo Liñán Cembrano (SBCCI, 2007)

A focal plane processor for continuous-time 1-D optical correlation applications. - Gustavo Liñán Cembrano; Luis Carranza; Betsaida Alexandre; Elisenda Roca; Ángel Rodríguez-Vázquez (ECCTD, 2009)

APS design alternatives in 0.18μm CMOS image sensor technology. - Sonia Vargas-Sierra; Elisenda Roca; Gustavo Liñán Cembrano (ECCTD, 2009)

Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas. - Rocío Maldonado-López; Fernando Vidal-Verdú; Gustavo Liñán; Ángel Rodríguez-Vázquez (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

In-pixel ADC for a vision architecture on CMOS-3D technology. - Manuel Suarez; Víctor M. Brea 001; Carlos M. Domínguez-Matas; Ricardo Carmona; Gustavo Liñán; Ángel Rodríguez-Vázquez (3DIC, 2010)

Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor. - Jorge Fernández-Berni; Ricardo Carmona-Galán; Gustavo Liñán Cembrano; Ákos Zarándy; Ángel Rodríguez-Vázquez (ICDSC, 2011)

Demo: Real-time remote reporting of active regions with Wi-FLIP. - Jorge Fernández-Berni; Ricardo Carmona-Galán; Gustavo Liñán Cembrano; Ákos Zarándy; Ángel Rodríguez-Vázquez (ICDSC, 2011)

A 176×144 148dB adaptive tone-mapping imager. - Sonia Vargas-Sierra; Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez (Sensors, Cameras, and Systems for Industrial and Scientific Applications, 2012)

Control and acquisition system for a High Dynamic Range CMOS Image Sensor. - Sonia Vargas-Sierra; Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez (ICECS, 2012)

A 148dB focal-plane tone-mapping QCIF imager. - Sonia Vargas-Sierra; Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez (ISCAS, 2012)

CMOS-3D Smart Imager Architectures for Feature Detection. - Manuel Suarez; Víctor M. Brea 001; Jorge Fernández-Berni; Ricardo Carmona-Galán; Gustavo Liñán; Diego Cabello; Ángel Rodríguez-Vázquez (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips. - Ricardo Carmona-Galán; Ákos Zarándy; Csaba Rekeczky; Péter Földesy; Alberto Rodríguez-Pérez; Carlos M. Domínguez-Matas; Jorge Fernández-Berni; Gustavo Liñán Cembrano; Maria Belen Pérez-Verdú; Zoltán Kárász; Manuel Suárez-Cambre; Víctor Manuel Brea Sánchez; et al. (J. Syst. Archit., 2013)

Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression. - Sonia Vargas-Sierra; Gustavo Liñán Cembrano; Ángel Rodríguez-Vázquez (ISCAS, 2015)

AISAD: A User-Friedly AI-Assisted MATLAB Tool for the High-Level Design of ΣΔ Modulators. - P. Manrique-Merchán; Gustavo Liñán Cembrano; José M. de la Rosa 001 (DCIS, 2024)

Increasing the Accuracy of Spectrogram-based Spectrum Sensing Trained by a Deep Learning Network Using a Resnet-18 Model. - A. Rojas; Gordana Jovanovic-Dolecek; José M. de la Rosa 001; Gustavo Liñán Cembrano (DCIS, 2024)

Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks. - Gustavo Liñán Cembrano; José M. de la Rosa 001 (ISCAS, 2024)

Live Demonstration: Using ANNs to Predict the Evolution of Spectrum Occupancy. - Gustavo Liñán Cembrano; José M. de la Rosa 001 (ISCAS, 2024)

Deep Learning-Based Architecture for RF Frame Detection for CR Applications Using Spectrograms. - A. Rojas; Gustavo Liñán Cembrano; Gordana Jovanovic-Dolecek; José M. de la Rosa 001 (MWSCAS, 2024)

Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief. - Gustavo Liñán Cembrano; Nuno Lourenço 003; Nuno Horta; José M. de la Rosa 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators. - Pablo Díaz-Lobo; Gustavo Liñán Cembrano; José M. de la Rosa 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Live Demonstration: AI-Assisted High-Level Design of Sigma-Delta Modulators. - P. Manrique-Merchán; Gustavo Liñán Cembrano; José M. de la Rosa 001 (ISCAS, 2025)

Live Demonstration: RF Frame Detection Using YOLOv8 for Spectrum Sensing. - A. Rojas; Gustavo Liñán Cembrano; Gordana Jovanovic-Dolecek; José M. de la Rosa 001 (ISCAS, 2025)

Spectrogram-Based Spectrum Prediction for AI-managed Cognitive-Radio Edge Devices. - A. Rojas; Gustavo Liñán Cembrano; Gordana Jovanovic-Dolecek; José M. de la Rosa 001 (ISCAS, 2025)

Combining Machine Learning and Optimization Techniques for the High-Level Design of Σ∆Ms. - Gustavo Liñán Cembrano; José M. de la Rosa 001 (SMACD, 2025)