FSM Decomposition for Low Power in FPGA. - Gustavo Sutter 001; Elias Todorovich; Sergio López-Buedo; Eduardo I. Boemo (FPL, 2002)

A Tool for Activity Estimation in FPGAs. - Elias Todorovich; M. Gilabert; Gustavo Sutter 001; Sergio López-Buedo; Eduardo I. Boemo (FPL, 2002)

Low-Power FSMs in FPGA: Encoding Alternatives. - Gustavo Sutter 001; Elias Todorovich; Sergio López-Buedo; Eduardo I. Boemo (PATMOS, 2002)

Comparative Study of SRT-Dividers in FPGA. - Gustavo Sutter 001; Gery Bioul; Jean-Pierre Deschamps (FPL, 2004)

Power Aware Dividers in FPGA. - Gustavo Sutter 001; Jean-Pierre Deschamps; Gery Bioul; Eduardo I. Boemo (PATMOS, 2004)

Finite Field Division Implementation. - Jean-Pierre Deschamps; Gustavo Sutter 001 (FPL, 2005)

Selected Papers from SPL 2008: Programmable Logic and Applications. - Gustavo Sutter 001; Richard Katz (Int. J. Reconfigurable Comput., 2008)

High speed fixed point dividers for FPGAs. - Gustavo Sutter 001; Jean-Pierre Deschamps (FPL, 2009)

A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. - Carlos Minchola; Gustavo Sutter 001 (ReConFig, 2009)

FPGA Implementations of BCD Multipliers. - Gustavo Sutter 001; Elias Todorovich; Gery Bioul; Martín Vázquez 001; Jean-Pierre Deschamps (ReConFig, 2009)

Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. - Martín Vázquez 001; Gustavo Sutter 001; Gery Bioul; Jean-Pierre Deschamps (ReConFig, 2009)

Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. - Gustavo Sutter 001; Jean-Pierre Deschamps; José Luis Imaña (FPL, 2010)

High-Speed FPGA 10's Complement Adders-Subtractors. - Gery Bioul; Martín Vázquez 001; Jean-Pierre Deschamps; Gustavo Sutter 001 (Int. J. Reconfigurable Comput., 2010)

High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. - Diego Sanchez-Roman; Gustavo Sutter 001; Sergio López-Buedo; Iván González 004; Francisco J. Gomez-Arribas; Javier Aracil 001; Francisco Palacios (IEEE Des. Test Comput., 2011)

Selected Papers from the Southern Programmable Logic Conference (SPL2010). - Elias Todorovich; Gustavo Sutter 001 (Int. J. Reconfigurable Comput., 2011)

Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. - Gustavo Sutter 001; Jean-Pierre Deschamps; José Luis Imaña (IEEE Trans. Ind. Electron., 2011)

Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. - Iván González 004; Sergio López-Buedo; Gustavo Sutter 001; Diego Sanchez-Roman; Francisco J. Gomez-Arribas; Javier Aracil 001 (J. Syst. Archit., 2012)

Guide to FPGA Implementation of Arithmetic Functions - Jean-Pierre Deschamps; Gustavo Sutter 001; Enrique Cantó (Springer, 2012)

Accurate and flexible flow-based monitoring for high-speed networks. - Marco Forconesi; Gustavo Sutter 001; Sergio López-Buedo; Javier Aracil 001 (FPL, 2013)

FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. - Diego Sanchez-Roman; Victor Moreno; Sergio López-Buedo; Gustavo Sutter 001; Iván González 004; Francisco J. Gomez-Arribas; Javier Aracil 001 (J. Syst. Archit., 2013)

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. - Gustavo Sutter 001; Jean-Pierre Deschamps; José Luis Imaña (IEEE Trans. Ind. Electron., 2013)

TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. - Jose Fernando Zazo; Marco Forconesi; Sergio López-Buedo; Gustavo Sutter 001; Javier Aracil 001 (ReConFig, 2014)

Bridging the gap between hardware and software open source network developments. - Marco Forconesi; Gustavo Sutter 001; Sergio López-Buedo; Jorge E. López de Vergara; Javier Aracil 001 (IEEE Netw., 2014)

Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. - Mario Ruiz; Gustavo Sutter 001; Sergio López-Buedo; Javier Ramos 002; Jorge E. López de Vergara; Javier Aracil 001 (ReConFig, 2015)

Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. - Mario Ruiz; Javier Ramos 002; Gustavo Sutter 001; Sergio López-Buedo; Jorge E. López de Vergara; C. Sisterna (FPL, 2016)

FPGA-based encrypted network traffic identification at 100 Gbit/s. - Mario Ruiz; Gustavo Sutter 001; Sergio López-Buedo; Jorge E. López de Vergara (ReConFig, 2016)

Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. - Jose Fernando Zazo; Sergio López-Buedo; Gustavo Sutter 001; Javier Aracil 001 (ReConFig, 2016)

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. - Mario Ruiz; Javier Ramos 002; Gustavo Sutter 001; Jorge E. López de Vergara; Sergio López-Buedo; Javier Aracil 001 (IEEE Commun. Mag., 2016)

An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. - Mario Ruiz; Gustavo Sutter 001; Sergio López-Buedo; Jose Fernando Zazo; Jorge E. López de Vergara (ReConFig, 2017)

A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. - Jose Fernando Zazo; Sergio López-Buedo; Mario Ruiz; Gustavo Sutter 001 (ReConFig, 2017)

Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip. - Tobias Alonso; Mario Ruiz; Angel Lopez Garcia-Arias; Gustavo Sutter 001; Jorge E. López de Vergara (FPL, 2018)

FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. - Gustavo Sutter 001; Mario Ruiz; Sergio López-Buedo; Gustavo Alonso (ReConFig, 2018)

Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. - Mario Ruiz; David Sidler; Gustavo Sutter 001; Gustavo Alonso; Sergio López-Buedo (FPL, 2019)

Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. - Martín Vázquez 001; Lucas Leiva; Gustavo Sutter 001 (Microprocess. Microsystems, 2019)

LOCO-ANS: An Optimization of JPEG-LS Using an Efficient and Low-Complexity Coder Based on ANS. - Tobias Alonso; Gustavo Sutter 001; Jorge E. López de Vergara (IEEE Access, 2021)

Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. - Tobias Alonso; Gustavo Sutter 001; Sergio López-Buedo; Jorge E. López de Vergara (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Detecting Malware in Encrypted Network Traffic Using Machine Learning and TLS Fingerprints. - Eduardo Polo-Peyres; Jorge E. López de Vergara; Gustavo Sutter 001; Iván González 004; Luis de Pedro (UCAmI (2), 2025)