A Comparison Between Testability Measures Applied to Complex Gates. - José Luís Güntzel; Gustavo Wilke; Márcio Bystronski; Ana Cristina Medina Pinto; Ricardo Reis 001 (LATW, 2002)

Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. - Gustavo Wilke; José Luís Güntzel; Márcio Bystronski; Ana Cristina Medina Pinto; Ricardo Reis 001 (SBCCI, 2002)

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. - David Guerrero Martos; Gustavo Wilke; José Luís Almada Güntzel; Manuel J. Bellido; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Alejandro Millán 001 (PATMOS, 2003)

Improving Critical Path Identification in Functional Timing Analysis. - Daniel Lima Ferrão; Gustavo Wilke; Ricardo Augusto da Luz Reis; José Luís Almada Güntzel (SBCCI, 2003)

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. - Cristiano Santos; Gustavo Wilke; Cristiano Lazzari; Ricardo Reis 001; José Luís Almada Güntzel (SBCCI, 2003)

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. - Gustavo Wilke; Ricardo Reis 001 (ISVLSI, 2008)

A novel scheme to reduce short-circuit power in mesh-based clock architectures. - Gustavo Wilke; Renan Fonseca; Cecilia Mezzomo; Ricardo Reis 001 (SBCCI, 2008)

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits. - Sandro Sawicki; Gustavo Wilke; Marcelo O. Johann; Ricardo Reis 001 (ICECS, 2009)

Non-uniform clock mesh optimization with linear programming buffer insertion. - Matthew R. Guthaus; Gustavo Wilke; Ricardo Reis 001 (DAC, 2010)

A study on layout quality of automatic generated cells. - Gracieli Posser; Adriel Ziesemer; Daniel Guimares Jr.; Gustavo Wilke; Ricardo A. L. Reis (ICECS, 2010)

A Mesh-Buffer Displacement Optimization Strategy. - Guilherme Flach; Gustavo Wilke; Marcelo O. Johann; Ricardo Reis 001 (ISVLSI, 2010)

Variability-aware physical design techniques. - Gustavo Wilke; Ricardo Reis 001 (LATW, 2010)

3D-Via Driven Partitioning for 3D VLSI Integrated Circuits. - Sandro Sawicki; Gustavo Wilke; Marcelo O. Johann; Ricardo Reis 001 (CLEI Electron. J., 2010)

Gate Sizing Minimizing Delay and Area. - Gracieli Posser; Guilherme Flach; Gustavo Wilke; Ricardo Reis 001 (ISVLSI, 2011)

Transistor sizing and gate sizing using geometric programming considering delay minimization. - Gracieli Posser; Guilherme Flach; Gustavo Wilke; Ricardo Reis 001 (NEWCAS, 2012)

High-performance clock mesh optimization. - Matthew R. Guthaus; Xuchu Hu; Gustavo Wilke; Guilherme Flach; Ricardo Reis 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Revisiting automated physical synthesis of high-performance clock networks. - Matthew R. Guthaus; Gustavo Wilke; Ricardo Reis 001 (ACM Trans. Design Autom. Electr. Syst., 2013)