Built-in self-test of a CMOS ALU. - Eduard Cerny; El Mostapha Aboulhamid; Guy Bois; Jocelyn Cloutier (IEEE Des. Test, 1988)

A Fast Low-Power Driver for Long Interconnections in VLSI Systems. - Mohamed Nekili; Yvon Savaria; Guy Bois (ISCAS, 1994)

Efficient generation of diagonal constraints for 2-D mask compaction. - Guy Bois; Eduard Cerny (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. - Mohamed Nekili; Guy Bois; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. - Manoucher Shaditalab; Guy Bois; Mohamad Sawan (FCCM, 1998)

Design of Clock Distribution Networks in Presence of Process Variations. - Mohamed Nekili; Yvon Savaria; Guy Bois (Great Lakes Symposium on VLSI, 1998)

Development of a high performance TSPC library for implementation of large digital building blocks. - B. Le Chapelain; A. Mechain; Yvon Savaria; Guy Bois (ISCAS (1), 1999)

Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. - Mohamed Nekili; Yvon Savaria; Guy Bois (IEEE J. Solid State Circuits, 1999)

Reconfigurable pipelined 2-D convolvers for fast digital signal processing. - B. Bosi; Guy Bois; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A methodology for interfacing open source systemC with a third party software. - Luc Charest; Michel Reid; El Mostapha Aboulhamid; Guy Bois (DATE, 2001)

Minimizing process-induced skew using delay tuning. - Mohamed Nekili; Yvon Savaria; Guy Bois (ISCAS (4), 2001)

Applying Multi-Paradigm and Design Pattern Approaches to Hardware/Software Design and Reuse. - Luc Charest; El Mostapha Aboulhamid; Guy Bois (Patterns and Skeletons for Parallel and Distributed Computing, 2003)

A methodology for the design of AHB bus master wrappers. - Marc Bertola; Guy Bois (DSD, 2003)

SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. - Jérôme Chevalier; Mathieu Rondonneau; Olivier Benny; Guy Bois; El Mostapha Aboulhamid; François R. Boyer (FDL, 2003)

Automating Functional Coverage Analysis Based on an Executable Specification. - S. Regimbal; Jean-Francois Lemire; Yvon Savaria; Guy Bois; El Mostapha Aboulhamid; A. Baron (IWSOC, 2003)

Teaching Bus Architectures with a Basic, Hands-On SOC Platform. - Marc Bertola; Guy Bois (MSE, 2003)

.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. - James Lapalme; El Mostapha Aboulhamid; Gabriela Nicolescu; Luc Charest; François R. Boyer; J. P. David; Guy Bois (DATE, 2004)

A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. - D. Quinn; Bruno Lavigueur; Guy Bois; El Mostapha Aboulhamid (DATE, 2004)

Using Design Patterns for Type Unification and Introspection in SystemC. - Luc Charest; El Mostapha Aboulhamid; Guy Bois (IWSOC, 2004)

Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. - S. Regimbal; Yvon Savaria; Guy Bois (IWSOC, 2004)

ESys.Net: a new solution for embedded systems modeling and simulation. - James Lapalme; El Mostapha Aboulhamid; Gabriela Nicolescu; Luc Charest; François R. Boyer; J. P. David; Guy Bois (LCTES, 2004)

A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. - Alena Tsikhanovich; El Mostapha Aboulhamid; Guy Bois (IWSOC, 2005)

A Reprogrammable SoC Design for a Real-Time Control Application. - Jean-Francois Thibeault; Mortimer Hubin; François Deslauriers; Patrick Samson; Guy Bois (MSE, 2005)

Transaction Level Modeling in Hardware/Software System Design using .Net Framework. - Alena Tsikhanovich; Frédéric Rousseau 001; El Mostapha Aboulhamid; Guy Bois (CCECE, 2006)

A practical approach for monitoring analog circuits. - Mohamed H. Zaki; Sofiène Tahar; Guy Bois (ACM Great Lakes Symposium on VLSI, 2006)

Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (SiPS, 2006)

Integration of Configurable Processors in a Multiprocessor Platform. - Simon Provost; Bruno Lavigueur; Guy Bois; Gabriela Nicolescu (SoCC, 2006)

A SystemC Refinement Methodology for Embedded Software. - Jérôme Chevalier; Maxime de Nanclas; Luc Filion; Olivier Benny; Mathieu Rondonneau; Guy Bois; El Mostapha Aboulhamid (IEEE Des. Test Comput., 2006)

Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. - Laurent Moss; Maxime de Nanclas; Luc Filion; Sebastien Fontaine; Guy Bois; El Mostapha Aboulhamid (DATE, 2007)

Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. - Mohamed H. Zaki; Ghiath Al Sammane; Sofiène Tahar; Guy Bois (FMCAD, 2007)

A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (ICECS, 2007)

An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. - Karim Hadjiat; Francis St-Pierre; Guy Bois; Yvon Savaria; Michel Langevin; Pierre G. Paulin (ICECS, 2007)

Communication Structure Refinement using Temporal Constraints Analysis. - Alena Tsikhanovich; El Mostapha Aboulhamid; Guy Bois (ICECS, 2007)

Qualitative Abstraction based Verification for Analog Circuits. - Mohamed H. Zaki; Sofiène Tahar; Guy Bois (ISoLA, 2007)

Exploring ISS Abstractions for Embedded Software Design. - Sebastien Fontaine; Luc Filion; Guy Bois (DSD, 2008)

Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. - Sebastien Fontaine; Sylvain Goyette; J. M. Pierre Langlois; Guy Bois (ICCD, 2008)

Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology. - Laurent Moss; Marc-André Cantin; Guy Bois; El Mostapha Aboulhamid (IEEE International Workshop on Rapid System Prototyping, 2008)

Formal verification of analog and mixed signal designs: A survey. - Mohamed H. Zaki; Sofiène Tahar; Guy Bois (Microelectron. J., 2008)

Optimizing Configuration and Application Mapping for MPSoC Architectures. - Sébastien Le Beux; Gabriela Nicolescu; Guy Bois; Youcef Bouchebaba; Michel Langevin; Pierre G. Paulin (AHS, 2009)

Integrating Abstraction Techniques for Formal Verification of Analog Designs. - Mohamed H. Zaki; William Denman; Sofiène Tahar; Guy Bois (J. Aerosp. Comput. Inf. Commun., 2009)

Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. - Patrick Mahoney; Yvon Savaria; Guy Bois; Patrice Plante (Trans. High Perform. Embed. Archit. Compil., 2009)

High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (J. Signal Process. Syst., 2009)

IP characterization methodology for fast and accurate power consumption estimation at transactional level model. - Michel Rogers-Vallée; Marc-André Cantin; Laurent Moss; Guy Bois (ICCD, 2010)

A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC. - Sébastien Le Beux; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (ISCAS, 2010)

Multi-Optical Network-on-Chip for Large Scale MPSoC. - Sébastien Le Beux; Jelena Trajkovic; Ian O'Connor; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (IEEE Embed. Syst. Lett., 2010)

Combining mapping and partitioning exploration for NoC-based embedded systems. - Sébastien Le Beux; Guy Bois; Gabriela Nicolescu; Youcef Bouchebaba; Michel Langevin; Pierre G. Paulin (J. Syst. Archit., 2010)

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. - Sébastien Le Beux; Jelena Trajkovic; Ian O'Connor; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (DATE, 2011)

Customized embedded processor design for global photographic tone mapping. - Shervin Vakili; Diana Carolina Gil; J. M. Pierre Langlois; Yvon Savaria; Guy Bois (ICECS, 2011)

A novel low-overhead flexible instrumentation framework for virtual platforms. - Tennessee Carmel-Veilleux; Jean-François Boland; Guy Bois (International Symposium on Rapid System Prototyping, 2011)

Finite-precision error modeling using affine arithmetic. - Shervin Vakili; J. M. Pierre Langlois; Guy Bois (ICASSP, 2013)

Customised soft processor design: a compromise between architecture description languages and parameterisable processors. - Shervin Vakili; J. M. Pierre Langlois; Guy Bois (IET Comput. Digit. Tech., 2013)

Reduction methods for adapting optical network on chip topologies to 3D architectures. - Sébastien Le Beux; Ian O'Connor; Gabriela Nicolescu; Guy Bois; Pierre G. Paulin (Microprocess. Microsystems, 2013)

Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic. - Shervin Vakili; J. M. Pierre Langlois; Guy Bois (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. - Pascal Nsame; Guy Bois; Yvon Savaria (ICECS, 2014)

Adaptive real-time DSP acceleration for SoC applications. - Pascal Nsame; Guy Bois; Yvon Savaria (MWSCAS, 2014)

Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications. - Pascal Nsame; Guy Bois; Yvon Savaria (NATW, 2014)

Designing customized microprocessors for fixed-point computation. - Shervin Vakili; J. M. Pierre Langlois; Guy Bois (AHS, 2015)

Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. - Pascal Nsame; Guy Bois; Yvon Savaria (ISCAS, 2015)

Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. - Alexsandre B. Lacroix; J. M. Pierre Langlois; François-Raymond Boyer; Antoine Gosselin; Guy Bois (ANCS, 2016)

Architectural exploration and implementation of an image processing chain with SpaceStudio™. - Fellipe Montero; Guy Bois; Eric Jenn; Kevin Duplantier (FPL, 2016)

Accuracy-aware processor customisation for fixed-point arithmetic. - Shervin Vakili; J. M. Pierre Langlois; Guy Bois (IET Comput. Digit. Tech., 2016)

Avionics Graphics Hardware Performance Prediction with Machine Learning. - Simon R. Girard; Vincent Legault; Guy Bois; Jean-François Boland (Sci. Program., 2019)

Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. - Julien Posso; Guy Bois; Yvon Savaria (ISCAS, 2022)

CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign. - Fabien Portas; Guy Bois; Yvon Savaria (NewCAS, 2024)

Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. - Julien Posso; Guy Bois; Yvon Savaria (NewCAS, 2024)

Real-Time Semantic Segmentation of Aerial Images Using an Embedded U-Net: A Comparison of CPU, GPU, and FPGA Workflows. - Julien Posso; Hugo Kieffer; Nicolas Menga; Omar Hlimi; Sébastien Tarris; Hubert Guerard; Guy Bois; Matthieu Couderc; Eric Jenn (CoRR, 2025)