Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. - Stephen Brown 003; Muhammad M. Khellah; Guy Lemieux (VLSI Design, 1996)

On two-step routing for FPGAS. - Guy G. Lemieux; Stephen Dean Brown; Daniel Vranesic (ISPD, 1997)

Design and Implementation of the NUMAchine Multiprocessor. - A. Grbic; Stephen Brown 003; S. Caranci; R. Grindley; M. Gusat; Guy G. Lemieux; K. Loveless; Naraig Manjikian; Sinisa Srbljic; Michael Stumm; Zvonko G. Vranesic; Zeljko Zilic (DAC, 1998)

Generating highly-routable sparse crossbars for PLDs. - Guy G. Lemieux; Paul Leventis; David M. Lewis (FPGA, 2000)

The NUMAchine Multiprocessor. - R. Grindley; Tarek S. Abdelrahman; Stephen Brown 003; S. Caranci; D. DeVries; Benjamin Gamsa; A. Grbic; M. Gusat; R. Ho; Orran Krieger; Guy G. Lemieux; K. Loveless; et al. (ICPP, 2000)

Using sparse crossbars within LUT. - Guy G. Lemieux; David M. Lewis (FPGA, 2001)

Circuit design of routing switches. - Guy G. Lemieux; David M. Lewis (FPGA, 2002)

Analytical Framework for Switch Block Design. - Guy G. Lemieux; David M. Lewis (FPL, 2002)

Design of interconnection networks for programmable logic. - Guy Lemieux; David A. Lewis (Kluwer, 2004)

Directional and single-driver wires in FPGA interconnect. - Guy Lemieux; Edmund Lee 002; Marvin Tom; Anthony J. Yu (FPT, 2004)

An improved "soft" eFPGA design and implementation strategy. - Victor O. Aken'Ova; Guy Lemieux; Resve A. Saleh (CICC, 2005)

Logic block clustering of large designs for channel-width constrained FPGAs. - Marvin Tom; Guy G. Lemieux (DAC, 2005)

Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. - Anthony J. Yu; Guy G. Lemieux (FPL, 2005)

FPGA Defect Tolerance: Impact of Granularity. - Anthony J. Yu; Guy G. Lemieux (FPT, 2005)

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. - David Grant; Scott Chin; Guy G. Lemieux (FPL, 2006)

Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route. - David Grant; Guy Lemieux (FPT, 2006)

Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. - Marvin Tom; David Leong; Guy G. Lemieux (ICCAD, 2006)

System-on-Chip: Reuse and Integration. - Resve A. Saleh; Steven J. E. Wilton; Shahriar Mirabbasi; Alan J. Hu; Mark R. Greenstreet; Guy Lemieux; Partha Pratim Pande; Cristian Grecu; André Ivanov (Proc. IEEE, 2006)

GlitchLess: an active glitch minimization technique for FPGAs. - Julien Lamoureux; Guy G. Lemieux; Steven J. E. Wilton (FPGA, 2007)

A Case for Soft Vector Processors in FPGAs. - Jason Yu; Guy Lemieux (FPT, 2007)

A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter. - Mehdi Alimadadi; Samad Sheikhaei; Guy Lemieux; Shahriar Mirabbasi; Patrick R. Palmer (ISSCC, 2007)

Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. - David Yeager; Darius Chiu; Guy G. Lemieux (SLIP, 2007)

A Survey and Taxonomy of GALS Design Styles. - Paul Teehan; Mark R. Greenstreet; Guy G. Lemieux (IEEE Des. Test Comput., 2007)

Extreme parallel architectures for the masses. - Tarek A. El-Ghazawi; Guy G. Lemieux (FPGA, 2008)

Designing with extreme parallelism. - Guy G. Lemieux; Tarek A. El-Ghazawi (FPGA, 2008)

Vector processing as a soft-core CPU accelerator. - Jason Yu; Guy G. Lemieux; Christopher Eagleston (FPGA, 2008)

PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters. - Johnny Tsung Lin Ho; Guy G. F. Lemieux (FPT, 2008)

Energy Recovery from High-Frequency Clocks Using DC-DC Converters. - Mehdi Alimadadi; Samad Sheikhaei; Guy Lemieux; Shahriar Mirabbasi; William G. Dunford; Patrick R. Palmer (ISVLSI, 2008)

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. - David Grant; Guy G. Lemieux (ACM Trans. Reconfigurable Technol. Syst., 2008)

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. - Julien Lamoureux; Guy G. Lemieux; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. - Edmund Lee 002; Guy Lemieux; Shahriar Mirabbasi (J. Signal Process. Syst., 2008)

PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. - Johnny Tsung Lin Ho; Guy G. Lemieux (FPGA, 2009)

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. - Paul Teehan; Guy G. Lemieux; Mark R. Greenstreet (FPGA, 2009)

Replace: An incremental placement algorithm for field programmable gate arrays. - David Leong; Guy G. Lemieux (FPL, 2009)

PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. - Xiao Dong; Guy G. F. Lemieux (FPT, 2009)

Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. - Paul Teehan; Guy G. Lemieux; Mark R. Greenstreet (NOCS, 2009)

Vector Processing as a Soft Processor Accelerator. - Jason Yu; Christopher Eagleston; Christopher Han-Yu Chou; Maxime Perreault; Guy G. Lemieux (ACM Trans. Reconfigurable Technol. Syst., 2009)

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). - Usman Ahmed; Guy G. Lemieux; Steven J. E. Wilton (FPGA, 2010)

A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid. - Mehdi Alimadadi; Samad Sheikhaei; Guy Lemieux; Shahriar Mirabbasi; William G. Dunford; Patrick R. Palmer (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

VEGAS: soft vector processor with scratchpad memory. - Christopher Han-Yu Chou; Aaron Severance; Alex D. Brant; Zhiduo Liu; Saurabh Sant; Guy G. Lemieux (FPGA, 2011)

A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. - David Grant; Chris C. Wang; Guy G. Lemieux (FPGA, 2011)

The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. - Jonathan Rose; Guy G. Lemieux (FPGA, 2011)

Scalable and deterministic timing-driven parallel placement for FPGAs. - Chris C. Wang; Guy G. Lemieux (FPGA, 2011)

Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. - Ameer Abdelhadi; Guy G. F. Lemieux (ReConFig, 2011)

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. - Jeffrey B. Goeders; Guy G. F. Lemieux; Steven J. E. Wilton (ReConFig, 2011)

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). - Usman Ahmed; Guy G. Lemieux; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2011)

ZUMA: An Open FPGA Overlay Architecture. - Alexander Brant; Guy G. F. Lemieux (FCCM, 2012)

Accelerator compiler for the VENICE vector processor. - Zhiduo Liu; Aaron Severance; Satnam Singh; Guy G. F. Lemieux (FPGA, 2012)

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. - Yehdhih Ould Mohammed Moctar; Nithin George; Hadi Parandeh-Afshar; Paolo Ienne; Guy G. F. Lemieux; Philip Brisk (FPGA, 2012)

Parallel FPGA placement based on individual LUT placement (abstract only). - Chris C. Wang; Guy G. F. Lemieux (FPGA, 2012)

Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. - Yehdhih Ould Mohammed Moctar; Guy G. F. Lemieux; Philip Brisk (FPL, 2012)

Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. - Alexander Brant; Ameer Abdelhadi; Aaron Severance; Guy G. F. Lemieux (FPT, 2012)

VENICE: A compact vector processor for FPGA applications. - Aaron Severance; Guy Lemieux (FPT, 2012)

Rapid Synthesis and Simulation of Computational Circuits in an MPPA. - David Grant; Graeme Smecher; Guy G. F. Lemieux; Rosemary Francis (J. Signal Process. Syst., 2012)

Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor. - Aaron Severance; Guy G. F. Lemieux (CODES+ISSS, 2013)

Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor. - Alexander Brant; Ameer Abdelhadi; Douglas H. H. Sim; Shao Lin Tang; Michael Xi Yue; Guy G. F. Lemieux (FCCM, 2013)

An efficient FPGA overlay for portable custom instruction set extensions. - Dirk Koch; Christian Beckhoff; Guy G. F. Lemieux (FPL, 2013)

TputCache: High-frequency, multi-way cache for high-throughput FPGA applications. - Aaron Severance; Guy G. F. Lemieux (FPL, 2013)

Modular multi-ported SRAM-based memories. - Ameer Abdelhadi; Guy G. F. Lemieux (FPGA, 2014)

Soft vector processors with streaming pipelines. - Aaron Severance; Joe Edwards; Hossein Omidian; Guy Lemieux (FPGA, 2014)

Deep and narrow binary content-addressable memories using FPGA-based BRAMs. - Ameer M. S. Abdelhadi; Guy G. F. Lemieux (FPT, 2014)

Modular SRAM-Based Binary Content-Addressable Memories. - Ameer M. S. Abdelhadi; Guy G. F. Lemieux (FCCM, 2015)

Rapid Overlay Builder for Xilinx FPGAs. - Michael Xi Yue; Dirk Koch; Guy G. F. Lemieux (FCCM, 2015)

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors. - Aaron Severance; Joe Edwards; Guy G. F. Lemieux (FPGA, 2015)

Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only). - Shao Lin S. T. Tang; Guy Lemieux (FPGA, 2015)

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. - Yehdhih Ould Mohammed Moctar; Guy G. F. Lemieux; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. - Ameer M. S. Abdelhadi; Guy G. F. Lemieux (FCCM, 2016)

Automated Space/Time Scaling of Streaming Task Graph. - Hossein Omidian; Guy G. F. Lemieux (CoRR, 2016)

Modular Switched Multiported SRAM-Based Memories. - Ameer M. S. Abdelhadi; Guy G. F. Lemieux (ACM Trans. Reconfigurable Technol. Syst., 2016)

Real-time object detection in software with custom vector instructions and algorithm changes. - Joe Edwards; Guy G. F. Lemieux (ASAP, 2017)

Exploring automated space/time tradeoffs for OpenVX compute graphs. - Hossein Omidian; Guy G. F. Lemieux (FPT, 2017)

Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. - Ameer M. S. Abdelhadi; Guy G. F. Lemieux; Lesley Shannon (FPL, 2018)

An Accelerated OpenVX Overlay for Pure Software Programmers. - Hossein Omidian; Nick Ivanov; Guy G. F. Lemieux (FPT, 2018)

DropBack: Continuous Pruning During Training. - Maximilian Golub; Guy Lemieux; Mieszko Lis (CoRR, 2018)

Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs. - Hossein Omidian; Guy G. F. Lemieux (FPL, 2019)

Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration. - Hossein Omidian; Guy G. F. Lemieux (HEART, 2019)

Full Deep Neural Network Training On A Pruned Weight Budget. - Maximilian Golub; Guy Lemieux; Mieszko Lis (SysML, 2019)

TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW. - Guy G. F. Lemieux; Joe Edwards; Joel Vandergriendt; Aaron Severance; Ryan De Iaco; Abdullah Raouf; Hussein Osman; Tom Watzka; Satwant Singh (CoRR, 2019)

Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training. - Dingqing Yang; Amin Ghasemazar; Xiaowei Ren; Maximilian Golub; Guy Lemieux; Mieszko Lis (MICRO, 2020)

Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training. - Mariko Tatsumi; Silviu-Ioan Filip; Caroline White; Olivier Sentieys; Guy Lemieux (FPT, 2022)

Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators. - May Young; Alan J. Hu; Guy G. F. Lemieux (ACM Trans. Embed. Comput. Syst., 2023)

MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing. - Zhonghua Zhou; Yuxuan Pan; Guy G. F. Lemieux; André Ivanov (ACM Trans. Design Autom. Electr. Syst., 2023)

Range Extension with Supernormals for Mixed-Precision 8-bit DNN Training. - Shing Wai Pun; Bozhang Bao; Silviu-Ioan Filip; Guy Lemieux; John V. Kim; Nazar Misyats; Nirvik Pande; Victor Ravain; Robert Sherrick (ARITH, 2025)

MPTorch-FPGA: A Custom Mixed-Precision Framework for FPGA-Based DNN Training. - Sami Ben Ali; Silviu-Ioan Filip; Olivier Sentieys; Guy G. Lemieux (DATE, 2025)