FOCUS: an experimental environment for validation of fault-tolerant systems - case study of a jet-engine controller. - Gwan Choi; Ravi K. Iyer; Victor Carreno (ICCD, 1989)

FOCUS: An Experimental Environment for Fault Sensitivity Analysis. - Gwan S. Choi; Ravishankar K. Iyer (IEEE Trans. Computers, 1992)

A Fast and Accurate Gate-Level Transient Fault Simulation Environment. - Hungse Cha; Elizabeth M. Rudnick; Gwan S. Choi; Janak H. Patel; Ravishankar K. Iyer (FTCS, 1993)

Wear-Out Simulation Environment for VLSI Designs. - Gwan S. Choi; Ravishankar K. Iyer (FTCS, 1993)

Fault behavior dictionary for simulation of device-level transients. - Gwan S. Choi; Ravishankar K. Iyer; Daniel G. Saab (ICCAD, 1993)

Device-Level Transient Fault Modeling. - Gregory L. Ries; Gwan S. Choi; Ravishankar K. Iyer (FTCS, 1994)

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. - Hungse Cha; Elizabeth M. Rudnick; Janak H. Patel; Ravishankar K. Iyer; Gwan S. Choi (IEEE Trans. Computers, 1996)

On-Chip Cache Memory Resilience. - Seung H. Hwang; Gwan S. Choi (HASE, 1998)

Error and Failure Analysis of a UNIX Server. - Ronjeet Lal; Gwan S. Choi (HASE, 1998)

Selective-set-invalidation (SSI) for soft-error-resilient cache architecture. - Seung H. Hwang; Gwan S. Choi (SIGARCH Comput. Archit. News, 1999)

Si-emulation: system verification using simulation and emulation. - Zan Yang; Byeong Min; Gwan Choi (ITC, 2000)

A Reliability Testing Environment for Off-the-Shelf Memory Subsystems. - Seung H. Hwang; Gwan S. Choi (IEEE Des. Test Comput., 2000)

Verification Simulation Acceleration Using Code-Perturbation. - Byeong Min; Gwan Choi (J. Electron. Test., 2000)

RTL functional verification using excitation and observation coverage. - Byeong Min; Gwan Choi (HLDVT, 2001)

An On-Line Testing Approach Using Code-Perturbation. - Zan Yang; Gwan Choi (IOLTW, 2001)

Simulation Using Code-Perturbation: Black- and White-Box Approach. - Zan Yang; Byeong Min; Gwan Choi (ISQED, 2001)

ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation. - Byeong Min; Gwan Choi (PRDC, 2001)

Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels. - Anand Selvarathinam; Euncheol Kim; Gwan Choi (ICCD, 2003)

A massively scaleable decoder architecture for low-density parity-check codes. - Anand Selvarathinam; Gwan Choi; Krishna Narayanan; Achal Prabhakar; Euncheol Kim (ISCAS (2), 2003)

An LDPC decoding schedule for memory access reduction. - Kiran K. Gunnam; Gwan Choi; Mark Yeary (ICASSP (5), 2004)

Fast Simulation Technique for LDPC Code Analysis. - Rajeshwary Tayade; Gwan Choi (International Conference on Wireless Networks, 2004)

Scaleable check node centric architecture for LDPC decoder. - Rohit Singhal; Gwan S. Choi; Nathan Mickler; Prabhavati Koteeswaran (ISCAS (4), 2004)

FPGA based implementation of decoder for array low-density parity-check codes. - Pankaj Bhagawat; Momin Uppal; Gwan Choi (ICASSP (5), 2005)

Quantized LDPC decoder design for binary symmetric channels. - Rohit Singhal; Gwan S. Choi; Rabi N. Mahapatra (ISCAS (6), 2005)

A design approach for radiation-hard digital electronics. - Rajesh Garg; Nikhil Jayakumar; Sunil P. Khatri; Gwan Choi (DAC, 2006)

Timing Failure Analysis of Commercial CPUs Under Operating Stress. - Sanghoan Chang; Gwan Choi (DFT, 2006)

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes. - Euncheol Kim; Nikhil Jayakumar; Pankaj Bhagawat; Anand Selvarathinam; Gwan Choi; Sunil P. Khatri (ICASSP (3), 2006)

Information theoretic approach to address delay and reliability in long on-chip interconnects. - Rohit Singhal; Gwan S. Choi; Rabi N. Mahapatra (ICCAD, 2006)

Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk. - Rohit Singhal; Gwan S. Choi; Rabi N. Mahapatra (ISQED, 2006)

Programmable LDPC Decoder Based on the Bubble-Sort Algorithm. - Rohit Singhal; Gwan S. Choi; Rabi N. Mahapatra (VLSI Design, 2006)

Minimum-energy LDPC decoder for real-time mobile application. - Weihuang Wang; Gwan Choi (DATE, 2007)

An FPGA Implementation of Dirty Paper Precoder. - Pankaj Bhagawat; Weihuang Wang; Momin Uppal; Gwan Choi; Zixiang Xiong; Mark B. Yeary; Alan Harris (ICC, 2007)

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax. - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary; Mohammed Atiquzzaman (ICC, 2007)

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard. - Kiran K. Gunnam; Gwan Choi; Weihuang Wang; Mark B. Yeary (ISCAS, 2007)

Speculative Energy Scheduling for LDPC Decoding. - Weihuang Wang; Gwan Choi (ISQED, 2007)

Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. - Sanghoan Chang; Gwan Choi (VLSI Design, 2007)

A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes. - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary (VLSI Design, 2007)

High performance on the fly reconfigurable MIMO detector. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (ACSCC, 2008)

Next generation iterative LDPC solutions for magnetic recording storage. - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary; Shaohua Yang; Yuanxing Lee (ACSCC, 2008)

Dynamically reconfigurable soft output MIMO detector. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (ICCD, 2008)

Architecture for reconfigurable MIMO detector and its FPGA implementation. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (ICECS, 2008)

Data Handling Limits of On-Chip Interconnects. - Rohit Singhal; Gwan Choi; Rabi N. Mahapatra (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study. - Pankaj Bhagawat; Rajballav Dash; Gwan S. Choi (ASP-DAC, 2009)

Systolic like soft-detection architecture for 4×4 64-QAM MIMO system. - Pankaj Bhagawat; Rajballav Dash; Gwan Choi (DATE, 2009)

SEU hardened clock regeneration circuits. - Rajballav Dash; Rajesh Garg; Sunil P. Khatri; Gwan S. Choi (ISQED, 2009)

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels. - Weihuang Wang; Gwan S. Choi; Kiran K. Gunnam (VLSI Design, 2009)

Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes". - Kiran K. Gunnam; Gwan S. Choi; Mark B. Yeary (EURASIP J. Embed. Syst., 2009)

Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. - Weihuang Wang; Euncheol Kim; Kiran K. Gunnam; Gwan S. Choi (J. Low Power Electron., 2009)

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. - Rajesh Garg; Nikhil Jayakumar; Sunil P. Khatri; Gwan S. Choi (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. - Tushar N. K. Jain; Paul V. Gratz; Alexander Sprintson; Gwan Choi (NOCS, 2010)

Low-power baseband processing for wireless multimedia systems using unequal error protection. - Yoon Seok Yang; Gwan Choi (WTS, 2010)

Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system. - Yoon Seok Yang; Pankaj Bhagawat; Gwan Choi (DAC, 2011)

Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs. - Reeshav Kumar; Yoon Seok Yang; Gwan Choi (VLSI Design, 2011)

Low-Power, Resilient Interconnection with Orthogonal Latin Squares. - Seung Eun Lee; Yoon Seok Yang; Gwan S. Choi; Wei Wu; Ravi R. Iyer 001 (IEEE Des. Test Comput., 2011)

Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture. - Yoon Seok Yang; Gwan Choi (Int. J. Inf. Technol. Commun. Convergence, 2011)

Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. - Tushar N. K. Jain; Mukund Ramakrishna; Paul V. Gratz; Alexander Sprintson; Gwan Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router. - Yoon Seok Yang; Hrishikesh Deshpande; Gwan S. Choi; Paul Gratz (ISCAS, 2012)

Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems. - Yoon Seok Yang; Gwan Choi (ACM Trans. Embed. Comput. Syst., 2012)

Bidirectional interconnect design for low latency high bandwidth NoC. - Reeshav Kumar; Hrishikesh Deshpande; Gwan S. Choi; Alexander Sprintson; Paul Gratz (ICICDT, 2013)

Support Vector Machine Based Detection of Drowsiness Using Minimum EEG Features. - Shaoda Yu; Peng Li 001; Honghuang Lin; Ehsan Rohani; Gwan Choi; Botang Shao; Qian Wang 003 (SocialCom, 2013)

An iterative soft decision based adaptive K-best decoder without SNR estimation. - Mehnaz Rahman; Ehsan Rohani; Gwan S. Choi (ACSSC, 2014)

Asynchronous design for precision-scaleable energy-efficient LDPC decoder. - Jingwei Xu 003; Tiben Che; Ehsan Rohani; Gwan Choi (ACSSC, 2014)

Signal reconstruction processor design for compressive sensing. - Jingwei Xu 003; Ehsan Rohani; Mehnaz Rahman; Gwan Choi (ISCAS, 2014)

Asynchronous baseband processor design for cooperative MIMO satellite communication. - Ehsan Rohani; Jingwei Xu 003; Tiben Che; Mehnaz Rahman; Gwan Choi; Mi Lu (MWSCAS, 2014)

WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture. - Yoon Seok Yang; Reeshav Kumar; Gwan S. Choi; Paul V. Gratz (ACM Trans. Design Autom. Electr. Syst., 2014)

XJ-BP: Express Journey Belief Propagation Decoding for Polar Codes. - Jingwei Xu 003; Tiben Che; Gwan S. Choi (GLOBECOM, 2015)

An iterative LR-aided MMSE extended soft MIMO decoding algorithm. - Mehnaz Rahman; Ehsan Rohani; Gwan S. Choi (ICNC, 2015)

Compressive sensing and reception for MIMO-OFDM based cognitive radio. - Jingwei Xu 003; Gwan S. Choi (ICNC, 2015)

Fixed Point Realization of Iterative LR-Aided Soft MIMO Decoding Algorithm. - Mehnaz Rahman; Gwan S. Choi (CoRR, 2015)

Accelerated Dual-Path Asynchronous Circuit. - Tiben Che; Jingwei Xu 003; Gwan Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

TC: Throughput centric successive cancellation decoder hardware implementation for polar codes. - Tiben Che; Jingwei Xu 003; Gwan S. Choi (ICASSP, 2016)

Overlapped list successive cancellation approach for hardware efficient polar code decoder. - Tiben Che; Jingwei Xu 003; Gwan S. Choi (ISCAS, 2016)

An Efficient Partial Sums Generator for Constituent Code based Successive Cancellation Decoding of Polar Codes. - Tiben Che; Gwan S. Choi (CoRR, 2016)

An Encoding Scheme with Constituent Codes Optimization for Polar Code-Aim to Reduce the Decoding Latency. - Tiben Che; Gwan S. Choi (CoRR, 2016)

Hardware Architecture of Complex K-best MIMO Decoder. - Mehnaz Rahman; Gwan S. Choi (CoRR, 2016)

The Normalized Singular Value Decomposition of Non-Symmetric Matrices Using Givens fast Rotations. - Ehsan Rohani; Gwan Choi; Mi Lu (CoRR, 2017)

SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. - Yoon Seok Yang; Hrishikesh Deshpande; Gwan Choi; Paul V. Gratz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

LISR: Image Super-resolution under Hardware Constraints. - Pravir Singh Gupta; Xin Yuan 002; Gwan Seong Choi (CoRR, 2019)

Drcas: Deep Restoration Network For Hardware Based Compressive Acquisition Scheme. - Pravir Singh Gupta; Xin Yuan 002; Gwan Seong Choi (ICIP, 2020)

CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency. - Sina Pourjabar; Gwan S. Choi (J. Signal Process. Syst., 2021)

A high-throughput multimode low-density parity-check decoder for 5G New Radio. - Sina Pourjabar; Gwan S. Choi (Int. J. Circuit Theory Appl., 2022)