A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator. - Gwangmyeong An; Juneho Yoon; Taeho Kim; Hyunsu Jang; Myeongju Park; Bongsu Kim; Jongchan An; Junyoung Song (ISOCC, 2023)

A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. - Jongchan An; Seung-Myeong Yu; Gwangmyeong An; Bongsu Kim; Hyunsu Jang; Sewook Hwang; Junyoung Song (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector. - Jongchan An; Seung-Myeong Yu; Gwangmyeong An; Songi Cheon; Hyunsu Jang; Junyoung Song (IEEE Trans. Circuits Syst. II Express Briefs, 2025)