Memory accesses management during high level synthesis. - Gwenolé Corre; Eric Senn; Pierre Bomel; Nathalie Julien; Eric Martin 001 (CODES+ISSS, 2004)

Memory Aware HLS and the Implementation of Ageing Vectors. - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (DSD, 2004)

A memory aware behavioral synthesis tool for real-time VLSI circuits. - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (ACM Great Lakes Symposium on VLSI, 2004)

A Memory Aware High Level Synthesis Tool . - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (ISVLSI, 2004)

A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. - Philippe Coussy; Gwenolé Corre; Pierre Bomel; Eric Senn; Eric Martin 001 (ICASSP (5), 2005)

High-level synthesis under I/O timing and memory constraints. - Philippe Coussy; Gwenolé Corre; Eric Senn; Pierre Bomel; Eric Martin 001 (ISCAS (1), 2005)

Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power - Gwenolé Corre; Nathalie Julien; Eric Senn; Eric Martin 001 (CoRR, 2006)

A Memory Aware High Level Synthesis Too - Gwenolé Corre; Nathalie Julien; Eric Senn; Eric Martin 001 (CoRR, 2006)

Memory Aware High-Level Synthesis for Embedded Systems - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (CoRR, 2006)

Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI - Gwenolé Corre; Philippe Coussy; Pierre Bomel; Eric Senn; Eric Martin 001 (CoRR, 2006)

Estimation et optimisation de la consommation des mémoires. - Gwenolé Corre; Eric Senn; Nathalie Julien; Eric Martin 001 (Tech. Sci. Informatiques, 2008)

Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. - Thomas Peyret; Gwenolé Corre; Mathieu Thevenin; Kevin J. M. Martin; Philippe Coussy (ASAP, 2014)

An automated design approach to map applications on CGRAs. - Thomas Peyret; Gwenolé Corre; Mathieu Thevenin; Kevin J. M. Martin; Philippe Coussy (ACM Great Lakes Symposium on VLSI, 2014)

A Scalable Design Approach to Efficiently Map Applications on CGRAs. - Satyajit Das; Thomas Peyret; Kevin J. M. Martin; Gwenolé Corre; Mathieu Thevenin; Philippe Coussy (ISVLSI, 2016)

Model-driven reliability evaluation for MPSoC design. - Tien Thanh Nguyen; Anthony Mouraud; Mathieu Thevenin; Gwenolé Corre; Olivier Pasquier; Sébastien Pillement (DASIP, 2017)

High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. - Tien Thanh Nguyen; Mathieu Thevenin; Anthony Mouraud; Gwenolé Corre; Olivier Pasquier; Sébastien Pillement (IPDPS Workshops, 2018)

A Comprehensive Survey of Visual SLAM Algorithms. - Andréa Macario Barros; Maugan Michel; Yoann Moline; Gwenolé Corre; Frédérick Carrel (Robotics, 2022)

FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic Scintillator. - Ali Hachem; Imane Belalchheb; Yoann Moline; Frédérick Carrel; Gwenolé Corre (NorCAS, 2023)