A hardware design approach for merge-sorting network. - Chun-Yueh Huang; Gwo-Jeng Yu; Bin-Da Liu (ISCAS (4), 2001)

The Implementation of an Amplitude-Locked Loop for Digital Communication Chip Design. - Gwo-Jia Jong; Yin-Chih Chen; Chen-Shen Huang; Gwo-Jeng Yu; Gwo-Jiun Horng (Wirel. Pers. Commun., 2013)

Artificial Neural Network Expert System for Integrated Heart Rate Variability. - Gwo-Jia Jong; Chen-Shen Huang; Gwo-Jeng Yu; Gwo-Jiun Horng (Wirel. Pers. Commun., 2014)