A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (A-SSCC, 2014)

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. - Woo-Rham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2014)

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS. - Gyu-Seob Jeong; Hankyu Chi; Kyungock Kim; Deog-Kyoon Jeong (ISCAS, 2014)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. - Kwanseo Park; Woo-Rham Bae; Haram Ju; Jinhyung Lee; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (ISCAS, 2015)

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (VLSIC, 2015)

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Sungchun Jang; Sungwoo Kim 001; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2015)

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. - Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. - Haram Ju; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. - Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS. - Yoonsoo Kim; Gyu-Seob Jeong; Jun-Eun Park; Joonbae Park; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Yoonsoo Kim; Hankyu Chi; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. - Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (Sensors, 2017)

A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. - Gyu-Seob Jeong; Wooseok Kim; Jaejin Park; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Sang-Hyeok Chu; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (BCICTS, 2018)

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS. - Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Gyu-Seob Jeong; Daehyun Koh; Seong Ho Park; Deog-Kyoon Jeong (ISLPED, 2018)

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Deog-Kyoon Jeong (VLSI Circuits, 2018)

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. - Hong-Seok Choi; Jeongho Hwang; Gyu-Seob Jeong; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Woo-Rham Bae; Jun-Eun Park; Chang-Soo Yoon; Jungmin Yoon; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. - Gyu-Seob Jeong; Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Daehyun Koh; Daeyoung Yun; Jinhyung Lee; Kwanseo Park; Han-Gon Ko; Kwangho Lee; Jiho Joo; Gyungock Kim; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. - Jeongho Hwang; Hyungrok Do; Hong-Seok Choi; Gyu-Seob Jeong; Daehyun Koh; Sungwoo Kim 001; Deog-Kyoon Jeong (OFC, 2019)

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. - Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Gyu-Seob Jeong; Daehyun Koh; Kwanseo Park; Sungwoo Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

Reference Spur Reduction Techniques for a Phase-Locked Loop. - Han-Gon Ko; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Access, 2019)

A Modulo-FIR Equalizer for Wireline Communications. - Gyu-Seob Jeong; Byungjun Kang; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. - Jeongho Hwang; Sang-Hyeok Chu; Gyu-Seob Jeong; Yeojoon Youn; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. - Byungjun Kang; Gyu-Seob Jeong; Jeongho Hwang; Kwanseo Park; Hyungrok Do; Hyojun Kim; Han-Gon Ko; Moon-Chul Choi; Deog-Kyoon Jeong (IEEE Access, 2021)