A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)

Sequential Anomaly Detection for Continuous Prediction of Unexpected ICU Admission From Emergency Department. - Sooho Choi; Gyumin Kim; Jeong Eul Kwon; Hyo Kyung Lee (IEEE Access, 2024)

Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs. - Gyumin Kim; Heechun Park (ASP-DAC, 2025)