An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction. - Chen Zhang; Gyunam Jeon; Yongsuk Choi; Yong-Bin Kim; Kyung Ki Kim (NATW, 2016)

Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. - Gyunam Jeon; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2017)

A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. - Gyunam Jeon; Yong-Bin Kim (ISCAS, 2017)

A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap. - Gyunam Jeon; Yong-Bin Kim (ISOCC, 2017)

Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor. - Gyunam Jeon; Yong-Bin Kim (MWSCAS, 2018)

Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. - Yongsuk Choi; Gyunam Jeon; Yong-Bin Kim (Integr., 2018)

Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. - Gyunam Jeon; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2019)

10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance. - Gyunam Jeon; Yong-Bin Kim (MWSCAS, 2019)

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. - Jaehyeok Yang; Hyeongjun Ko; Kyunghoon Kim; Hyunsu Park; Jihwan Park; Ji-Hyo Kang; Jin-Youp Cha; Seongjin Kim; Youngtaek Kim; Minsoo Park; Gangsik Lee; Keonho Lee; et al. (ISSCC, 2024)