The DIMM tree architecture: A high bandwidth and scalable memory system. - Kanit Therdsteerasukdi; Gyungsu Byun; Jeremy Ir; Glenn Reinman; Jason Cong; M. Frank Chang (ICCD, 2011)

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. - Gyungsu Byun; Yanghyo Kim; Jongsun Kim; Sai-Wang Tam; Hsieh-Hung Hsieh; P.-Y. Wu; Chewnpu Jou; Jason Cong; Glenn Reinman; Mau-Chung Frank Chang (ISSCC, 2011)

A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects. - Jongsun Kim; Gyungsu Byun; M. Frank Chang (IEICE Trans. Electron., 2011)

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. - Yanghyo Kim; Gyungsu Byun; Adrian Tang 002; Chewnpu Jou; Hsieh-Hung Hsieh; Glenn Reinman; Jason Cong; Mau-Chung Frank Chang (ISSCC, 2012)

Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. - Yanghyo Kim; Sai-Wang Tam; Gyungsu Byun; Hao Wu 026; Lan Nan; Glenn Reinman; Jason Cong; Mau-Chung Frank Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. - Kanit Therdsteerasukdi; Gyungsu Byun; Jeremy Ir; Glenn Reinman; Jason Cong; Mau-Chung Frank Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling. - Gyungsu Byun; Yanghyo Kim; Jongsun Kim; Sai-Wang Tam; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2012)

Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. - Kanit Therdsteerasukdi; Gyungsu Byun; Jason Cong; M. Frank Chang; Glenn Reinman (ACM Trans. Archit. Code Optim., 2012)

Reevaluating the latency claims of 3D stacked memories. - Daniel W. Chang; Gyungsu Byun; Hoyoung Kim; Minwook Ahn; Soojung Ryu; Nam Sung Kim; Michael J. Schulte (ASP-DAC, 2013)

Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems. - Hao Wang 011; Chang-Jae Park; Gyungsu Byun; Jung Ho Ahn; Nam Sung Kim (HPCA, 2015)