A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. - Soo-Min Lee; Jihoon Lim; Jaehyuk Jang; Hyoungjoong Kim; Kyunghwan Min; Woongki Min; Hyeonji Han; Gyusik Kim; Jaeyoung Kim; Chulho Kim; Sejun Jeon; Jinhoon Park; et al. (ESSCIRC, 2022)

A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS. - Kyungmin Lee; Jaehong Jung; Gyusik Kim; Joomyoung Kim; Seungjin Kim; Seunghyun Oh; Sung Min Park 001; Jongwoo Lee (A-SSCC, 2023)

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)