Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. - H. C. Srinivasaiah; Navakanta Bhat (ASP-DAC/VLSI Design, 2002)

Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. - H. C. Srinivasaiah; Navakanta Bhat (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. - H. C. Srinivasaiah; Navakanta Bhat (VLSI Design, 2004)

Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM. - H. C. Srinivasaiah (VLSI Design, 2012)

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. - M. C. Parameshwara; H. C. Srinivasaiah (J. Circuits Syst. Comput., 2017)