Low Power Reversible Parallel Binary Adder/Subtractor - H. G. Rangaraju; U. Venugopal; K. N. Muralidhara; K. B. Raja (CoRR, 2010)

Design of Efficient Reversible Multiplier. - H. G. Rangaraju; Aakash Babu Suresh; K. N. Muralidhara (ACITY (3), 2012)

Design and Performance Analysis of High Throughput and Low Power RNS-Based FIR Filter Design on FPGA. - B. N. Mohan Kumar; H. G. Rangaraju (Int. J. e Collab., 2022)

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks. - B. N. Mohan Kumar; H. G. Rangaraju (Int. J. Pervasive Comput. Commun., 2022)

Mobile Adaptive Routing Algorithm for Road-Aware Infrastructure-Assisted Communication in Cognitive Internet of Vehicles. - M. Divyashree; H. G. Rangaraju; C. R. Revanna (Int. J. Interact. Mob. Technol., 2024)